ARM UMC55ULP Sign-Off Guidelines and FFG/SSG Corner Availability
The ARM UMC55ULP sign-off guidelines explicitly recommend using only the Fast-Fast (FF) and Slow-Slow (SS) corners for design sign-off. However, the official Process Design Kit (PDK) provided by the foundry includes additional corners such as Fast-Fast Global (FFG) and Slow-Slow Global (SSG). This discrepancy raises questions about whether the FFG/SSG corners can be used for sign-off and what implications this might have on the design’s performance, power, and reliability.
The FF and SS corners are typically used to represent the best-case and worst-case scenarios for timing analysis. The FF corner represents the fastest process, voltage, and temperature (PVT) conditions, while the SS corner represents the slowest PVT conditions. These corners are essential for ensuring that the design meets timing requirements under all possible operating conditions.
The FFG and SSG corners, on the other hand, are global corners that account for variations across the entire die. These corners are used to model the impact of global process variations, such as those caused by wafer-level or lot-level variations, on the design’s performance. While the FFG/SSG corners provide a more comprehensive view of the design’s behavior under global variations, they are not explicitly mentioned in the ARM UMC55ULP sign-off guidelines.
The availability of FFG/SSG corners in the PDK suggests that the foundry considers these corners to be important for certain types of analysis. However, the absence of these corners in the ARM sign-off guidelines indicates that ARM may not have validated the UMC55ULP libraries under these conditions. This raises concerns about whether the FFG/SSG corners can be used for sign-off without compromising the design’s reliability.
Potential Risks of Using FFG/SSG Corners for Sign-Off
Using the FFG/SSG corners for sign-off without explicit validation from ARM could introduce several risks. First, the FFG/SSG corners may not accurately represent the worst-case or best-case scenarios for timing analysis. The global variations modeled by these corners may not align with the local variations that are more critical for timing closure. This could lead to optimistic or pessimistic timing results, depending on the specific characteristics of the design.
Second, the FFG/SSG corners may not have been fully characterized for power and reliability. The ARM UMC55ULP libraries are optimized for the FF and SS corners, and using the FFG/SSG corners could result in unexpected power consumption or reliability issues. For example, the FFG corner might lead to higher leakage currents, while the SSG corner might result in increased delay and power consumption.
Third, the use of FFG/SSG corners could complicate the sign-off process. The ARM UMC55ULP sign-off guidelines provide a clear framework for validating the design under the FF and SS corners. Deviating from these guidelines by using the FFG/SSG corners could require additional validation steps, such as custom characterization or simulation, to ensure that the design meets all performance, power, and reliability requirements.
Finally, there is a risk that the FFG/SSG corners may not be supported by all tools in the design flow. The ARM UMC55ULP libraries are typically integrated into Electronic Design Automation (EDA) tools that are optimized for the FF and SS corners. Using the FFG/SSG corners could require modifications to the tool settings or even custom scripts to ensure that the tools correctly interpret the libraries.
Recommended Approach for FFG/SSG Corner Validation and Sign-Off
Given the potential risks associated with using the FFG/SSG corners for sign-off, it is recommended to follow a cautious approach. The first step is to consult with ARM and the foundry to understand the rationale behind the inclusion of the FFG/SSG corners in the PDK and their absence in the ARM sign-off guidelines. This consultation should aim to clarify whether the FFG/SSG corners are intended for sign-off or for other types of analysis, such as yield optimization or reliability testing.
If the FFG/SSG corners are deemed necessary for sign-off, the next step is to perform a thorough characterization of the ARM UMC55ULP libraries under these corners. This characterization should include timing, power, and reliability analysis to ensure that the libraries meet the required specifications under the FFG/SSG conditions. The results of this characterization should be compared with the results obtained under the FF and SS corners to identify any discrepancies or potential issues.
Once the libraries have been characterized, the design should be re-validated under the FFG/SSG corners. This validation should include both static timing analysis (STA) and dynamic simulation to ensure that the design meets all timing, power, and reliability requirements. Any issues identified during this validation should be addressed through design modifications or additional characterization.
Finally, it is important to document the use of the FFG/SSG corners in the sign-off process. This documentation should include the rationale for using these corners, the results of the characterization and validation, and any modifications made to the design or tool settings. This documentation will be essential for ensuring that the design can be successfully manufactured and that it meets all performance, power, and reliability requirements.
In conclusion, while the FFG/SSG corners provide a more comprehensive view of the design’s behavior under global variations, their use for sign-off should be approached with caution. The potential risks associated with using these corners can be mitigated through careful characterization, validation, and documentation. By following this recommended approach, designers can ensure that their ARM UMC55ULP-based designs meet all performance, power, and reliability requirements, even when using the FFG/SSG corners for sign-off.
