ARM Cortex-A55 and FEAT_SHA3: Understanding the Limitations
The ARM Cortex-A55 is a mid-range, low-power processor core that implements the Armv8.2-A architecture. It is widely used in embedded systems and mobile devices due to its balance of performance and energy efficiency. However, there has been significant confusion regarding its support for the FEAT_SHA3 extension, which includes cryptographic instructions such as EOR3, RAX1, XAR, and BCAX. These instructions are part of the SHA-3 cryptographic algorithm, which is increasingly important for modern security applications.
The Cortex-A55 is documented to support extensions up to Armv8.2-A, with optional support for certain features from Armv8.3-A and Armv8.4-A. However, the FEAT_SHA3 extension, which is part of Armv8.4-A, is not natively supported by the Cortex-A55. This has led to misunderstandings, as some documentation suggests that the Cortex-A55 might support features beyond its stated architecture version. The confusion arises from the fact that the Cortex-A55 can implement certain optional extensions from later architectures, but this does not include FEAT_SHA3.
To clarify, the Cortex-A55 does not implement the FEAT_SHA3 extension. This is evident from the ARM documentation, which states that the Cortex-A55 supports only the base Armv8.2-A architecture with optional extensions from Armv8.3-A and Armv8.4-A. The FEAT_SHA3 extension is not among these optional features. Therefore, developers looking to leverage SHA-3 instructions must consider processors that natively support Armv8.4-A or later.
Misinterpretation of ARM Architecture Extensions and Cortex-A55 Capabilities
The confusion surrounding the Cortex-A55’s support for FEAT_SHA3 stems from a misinterpretation of ARM’s architecture extension rules. According to ARM’s documentation, an Armv8.x-A processor can implement features from the next .x extension (e.g., Armv8.2-A can implement Armv8.3-A features) but cannot implement features from any .x extension after that (e.g., Armv8.2-A cannot implement Armv8.4-A features). However, the Cortex-A55 documentation mentions support for certain Armv8.4-A features, such as the Dot Product instructions, which has led to the assumption that it might also support FEAT_SHA3.
This assumption is incorrect. The Cortex-A55’s support for specific Armv8.4-A features does not extend to FEAT_SHA3. The Dot Product instructions, for example, are part of the Armv8.4-A extension but are implemented as optional features in the Cortex-A55. FEAT_SHA3, on the other hand, is not listed as an optional feature in the Cortex-A55 documentation. This discrepancy highlights the importance of carefully reviewing the processor’s technical reference manual (TRM) and architecture documentation to understand its capabilities fully.
Another source of confusion is the ID_AA64ISAR0_EL1 register, which provides information about the instructions implemented in the AArch64 state. This register includes bit fields that indicate support for cryptographic extensions. In the case of the Cortex-A55, the ID_AA64ISAR0_EL1 register does not indicate support for FEAT_SHA3. Instead, it shows support for AES and SHA-2, which are part of the base Armv8.2-A architecture. This further confirms that the Cortex-A55 does not support the SHA-3 instructions.
Identifying Suitable Hardware and Workarounds for SHA-3 Instruction Testing
For developers who require SHA-3 instruction support, the Cortex-A55 is not a suitable choice. Instead, processors that implement Armv8.4-A or later should be considered. The Cortex-A75, for example, is a higher-performance core that supports Armv8.2-A with optional extensions from Armv8.3-A and Armv8.4-A. However, even the Cortex-A75 does not guarantee support for FEAT_SHA3, as this depends on the specific implementation by the SoC manufacturer.
To test SHA-3 instructions, developers should look for hardware platforms that explicitly state support for Armv8.4-A or later. Some examples include the Apple A12 Bionic and later Apple processors, which are known to implement Armv8.4-A features. Additionally, certain high-end Qualcomm Snapdragon and Samsung Exynos processors may also support FEAT_SHA3, depending on their implementation of the Armv8.4-A architecture.
If hardware with FEAT_SHA3 support is not available, developers can use software-based implementations of the SHA-3 algorithm. While this approach will not provide the same performance benefits as hardware-accelerated instructions, it allows for testing and development on existing hardware. Open-source libraries such as OpenSSL and libsodium provide software implementations of SHA-3 that can be used as a temporary solution until suitable hardware becomes available.
In conclusion, the Cortex-A55 does not support the FEAT_SHA3 extension, and developers should carefully review processor documentation to identify suitable hardware for SHA-3 instruction testing. For those unable to access Armv8.4-A hardware, software-based implementations offer a viable alternative for development and testing purposes.
