Estimating Memory Accesses from ARM Cortex-M33 Instruction Execution Using DWT Counters

ARM Cortex-M33 Instruction Fetch and Memory Access Relationship

The ARM Cortex-M33 processor, as implemented in the Arm Musca Board A1 with Corelink SSE 200 IP, features a dual-core architecture with a three-stage pipeline. One of the key aspects of debugging and tracing on this platform involves understanding the relationship between instruction execution and memory access. The Cortex-M33 fetches instructions in 32-bit chunks, but the Thumb instruction set used by the Cortex-M33 can include both 16-bit and 32-bit instructions. This variability complicates the direct correlation between instruction execution and memory access.

The Data Watchpoint and Trace (DWT) unit in the Cortex-M33 provides several counters that can be used to estimate the number of instructions executed, stalls, and other performance metrics. Specifically, the DWT_CPICNT counter can be used to measure the number of cycles spent on instruction fetch stalls. By combining this information with the total cycle count (CYCCNT) and other counters, it is possible to estimate the number of instructions executed. However, the relationship between instruction execution and memory access is not straightforward due to the variable instruction size and the potential for instruction cache hits and misses.

To estimate memory accesses, one must consider the instruction fetch behavior. Each fetch operation retrieves 32 bits of data, which could contain one 32-bit instruction or two 16-bit instructions. This means that the number of memory accesses required to fetch a given number of instructions can vary. Additionally, the presence of instruction cache can significantly reduce the number of memory accesses by serving repeated instruction fetches from the cache rather than main memory.

Instruction Fetch Variability and Memory Access Estimation Challenges

The primary challenge in estimating memory accesses from instruction execution lies in the variability of instruction sizes and the behavior of the instruction cache. The Cortex-M33 uses the Thumb-2 instruction set, which includes both 16-bit and 32-bit instructions. This means that a single 32-bit fetch operation could result in one 32-bit instruction or two 16-bit instructions being executed. This variability makes it difficult to directly correlate the number of instructions executed with the number of memory accesses.

Another factor to consider is the instruction cache. The Cortex-M33 includes an optional instruction cache that can significantly reduce the number of memory accesses by caching frequently accessed instructions. When an instruction is fetched from the cache, no memory access is required, which further complicates the estimation of memory accesses based on instruction execution.

The DWT counters provide some insight into the number of instructions executed and the number of stalls, but they do not directly measure memory accesses. The DWT_CPICNT counter measures the number of cycles spent on instruction fetch stalls, which can be used to infer the number of memory accesses if the cache behavior is known. However, without detailed knowledge of the cache hit rate and the distribution of instruction sizes, it is difficult to accurately estimate memory accesses.

Accurate Memory Access Estimation Using DWT Counters and Cache Analysis

To accurately estimate memory accesses from instruction execution on the Cortex-M33, a combination of DWT counters and cache analysis is required. The following steps outline a method for achieving this:

1. Measure Instruction Execution and Stalls: Use the DWT counters to measure the total number of cycles (CYCCNT), the number of instruction fetch stalls (DWT_CPICNT), and other relevant counters. This will provide an estimate of the number of instructions executed and the number of stalls due to instruction fetch.

2. Analyze Instruction Size Distribution: Analyze the distribution of instruction sizes in the code being executed. This can be done by disassembling the code and counting the number of 16-bit and 32-bit instructions. This information is necessary to estimate the number of memory accesses required to fetch the instructions.

3. Estimate Cache Hit Rate: Estimate the cache hit rate for the instruction cache. This can be done by running the code with the cache enabled and disabled and comparing the number of stalls and execution time. The cache hit rate can then be used to estimate the number of memory accesses that would have been required without the cache.

4. Calculate Memory Accesses: Using the information gathered from the DWT counters, instruction size distribution, and cache hit rate, calculate the estimated number of memory accesses. This can be done by first calculating the number of instruction fetches required based on the instruction size distribution, then adjusting for the cache hit rate to estimate the number of memory accesses.

For example, if the code being executed consists of 60% 16-bit instructions and 40% 32-bit instructions, and the cache hit rate is 80%, the number of memory accesses can be estimated as follows:

• Calculate the number of instruction fetches required: If 1000 instructions are executed, 600 are 16-bit and 400 are 32-bit. Each 32-bit fetch can contain two 16-bit instructions or one 32-bit instruction. Therefore, the number of fetches required is (600 / 2) + 400 = 700 fetches.
• Adjust for the cache hit rate: If the cache hit rate is 80%, then 20% of the fetches will result in memory accesses. Therefore, the estimated number of memory accesses is 700 * 0.2 = 140 memory accesses.

This method provides a more accurate estimate of memory accesses by taking into account the variability of instruction sizes and the impact of the instruction cache. However, it is important to note that this is still an estimate and may not be perfectly accurate due to factors such as branch prediction and out-of-order execution.

In conclusion, while it is possible to estimate memory accesses from instruction execution on the ARM Cortex-M33 using DWT counters, the process is complex and requires detailed analysis of instruction size distribution and cache behavior. By combining these factors, it is possible to achieve a reasonable estimate of memory accesses, but this estimate should be used with caution and validated against actual memory access measurements where possible.