ARM Cortex-M7 MPU Configuration: WBWA vs. Write-Through Cache Policy Conflict

ARM Cortex-M7 External RAM Cache Policy Discrepancy

The ARM Cortex-M7 processor, as used in the STM32F746 microcontroller, provides a Memory Protection Unit (MPU) that allows developers to configure memory regions with specific attributes, including cache policies. The default cache policy for the External RAM memory region (0x60000000 – 0x7FFFFFFF) is Write-Back Write-Allocate (WBWA), as documented in the ARM Cortex-M7 Generic User Guide. However, STMicroelectronics’ application note for the STM32F7 and STM32H7 series recommends configuring this region as Write-Through (WT) when interfacing with the Flexible Memory Controller (FMC) peripheral. This discrepancy raises questions about the correct cache policy for optimal performance and reliability.

The WBWA cache policy is designed to improve performance by reducing the number of writes to external memory. When a write operation occurs, the data is written to the cache, and the corresponding cache line is marked as dirty. The data is only written back to external memory when the cache line is evicted or explicitly flushed. This reduces the bandwidth required for write operations but introduces the risk of data inconsistency if the cache is not properly managed.

In contrast, the Write-Through cache policy ensures that every write operation is immediately propagated to external memory, while still allowing reads to be cached. This simplifies cache management and ensures data consistency but may increase the bandwidth required for write operations, potentially impacting performance.

The conflict between the ARM documentation and STMicroelectronics’ recommendation arises from the specific requirements of the FMC peripheral and the trade-offs between performance and data consistency. The FMC is used to interface with external memory devices such as SDRAM, SRAM, and NOR Flash, which may have different timing and reliability requirements. STMicroelectronics’ recommendation to use the Write-Through policy for the FMC region is likely based on the need to ensure data consistency and avoid potential issues with cache coherency.

Memory Protection Unit Override and FMC Peripheral Constraints

The ARM Cortex-M7 MPU allows developers to override the default memory access behavior, including the cache policy, for specific memory regions. This flexibility is essential for optimizing performance and ensuring reliable operation in complex embedded systems. However, it also introduces the potential for configuration errors and misunderstandings, particularly when dealing with peripherals like the FMC that have specific timing and coherency requirements.

The FMC peripheral in the STM32F746 microcontroller is designed to provide a high-speed interface to external memory devices. The timing requirements for these devices can be stringent, and the FMC must ensure that data is written to external memory in a timely manner to avoid data corruption or loss. The Write-Through cache policy is recommended for the FMC region because it ensures that data is immediately written to external memory, reducing the risk of data inconsistency due to delayed writes.

In addition to the cache policy, the MPU configuration for the FMC region must also consider other memory attributes, such as access permissions, shareability, and execute-never (XN) settings. These attributes can affect the performance and security of the system, and they must be carefully configured to meet the requirements of the application.

The STMicroelectronics application note provides an example MPU configuration for the FMC region, which includes the Write-Through cache policy. This example is intended to illustrate a typical configuration for the FMC peripheral, but it is not necessarily the only valid configuration. Developers must consider the specific requirements of their application and the characteristics of the external memory devices when configuring the MPU.

Implementing Optimal MPU Configuration for FMC and External RAM

To resolve the conflict between the ARM Cortex-M7 default cache policy and STMicroelectronics’ recommendation, developers must carefully evaluate the requirements of their application and the characteristics of the external memory devices. The following steps outline a systematic approach to configuring the MPU for the FMC region and external RAM:

1. Evaluate Application Requirements: Determine the performance and data consistency requirements of the application. Consider factors such as the frequency of write operations, the criticality of data consistency, and the timing requirements of the external memory devices.

2. Analyze External Memory Characteristics: Review the datasheets for the external memory devices to understand their timing and coherency requirements. Pay particular attention to the write timing parameters and any recommendations for cache policy.

3. Configure MPU Attributes: Based on the application requirements and external memory characteristics, configure the MPU attributes for the FMC region. Consider the following attributes:

   • Cache Policy: Choose between Write-Back Write-Allocate (WBWA) and Write-Through (WT) based on the trade-offs between performance and data consistency.
   • Access Permissions: Set the appropriate access permissions (e.g., read-only, read-write) for the FMC region.
   • Shareability: Configure the shareability attribute to ensure proper cache coherency in multi-core or DMA-enabled systems.
   • Execute-Never (XN): Set the XN attribute to prevent code execution from the FMC region, enhancing system security.

4. Test and Validate: Implement the MPU configuration and thoroughly test the system to ensure that it meets the performance and data consistency requirements. Use debugging tools and performance profiling to identify any issues and refine the configuration as needed.

5. Optimize for Performance: If the initial configuration meets the data consistency requirements but falls short of performance targets, consider optimizing the cache policy and other MPU attributes. For example, if the Write-Through policy is too slow, experiment with the Write-Back Write-Allocate policy and implement explicit cache management techniques (e.g., cache flushing) to ensure data consistency.

6. Document and Maintain: Document the final MPU configuration and the rationale behind the chosen attributes. This documentation will be valuable for future maintenance and troubleshooting.

By following these steps, developers can resolve the conflict between the ARM Cortex-M7 default cache policy and STMicroelectronics’ recommendation, ensuring optimal performance and reliable operation of the STM32F746 microcontroller in their embedded systems.

Example MPU Configuration for STM32F746 FMC Region

The following table provides an example MPU configuration for the FMC region in the STM32F746 microcontroller, based on the considerations outlined above:

This configuration is a starting point and should be adjusted based on the specific requirements of the application and the characteristics of the external memory devices.

Conclusion

The conflict between the ARM Cortex-M7 default cache policy and STMicroelectronics’ recommendation for the FMC region highlights the importance of careful MPU configuration in embedded systems. By understanding the trade-offs between performance and data consistency, and by systematically evaluating the requirements of the application and external memory devices, developers can implement an optimal MPU configuration that ensures reliable operation and maximizes performance. The example configuration provided in this guide serves as a starting point, but developers must tailor the MPU settings to the specific needs of their system.