ARM Cortex-A9 Dual-Core AMP Baremetal Execution Issues

The challenge of configuring an Asymmetric Multiprocessing (AMP) baremetal environment on an ARM Cortex-A9 dual-core SoC, such as the one found in the Terasic DE1-SoC, involves running two separate binaries on each core independently. This setup requires careful handling of core initialization, binary loading, and synchronization to ensure that each core executes its designated code without interfering with the other. The primary issue reported is that when CPU1 is released from reset, it executes code from random memory locations, leading to conflicts with CPU0. This behavior indicates a lack of proper initialization, memory mapping, or synchronization mechanisms between the two cores.

The ARM Cortex-A9 MPCore architecture supports both Symmetric Multiprocessing (SMP) and AMP configurations. In an AMP setup, each core operates independently, often running different operating systems or baremetal applications. However, achieving this requires precise control over the boot process, memory partitioning, and inter-core communication. The absence of these controls can result in undefined behavior, such as CPU1 executing incorrect code or accessing shared resources improperly.

Key technical aspects of this issue include:

  • The boot process of ARM Cortex-A9 cores, including the role of the reset vector and bootloader.
  • Memory mapping and partitioning for AMP configurations, ensuring that each core has access to its designated memory regions.
  • Synchronization mechanisms, such as spinlocks or mailboxes, to coordinate activities between cores.
  • Debugging techniques to trace the execution flow and identify where CPU1 deviates from its expected behavior.

Understanding these aspects is crucial for diagnosing and resolving the reported issues. The following sections will delve into the possible causes and provide detailed troubleshooting steps and solutions.

Improper Core Initialization and Memory Mapping

One of the primary causes of the reported issue is improper initialization of CPU1 and incorrect memory mapping. When CPU1 is released from reset, it begins executing code from its reset vector. If the reset vector or the memory map is not configured correctly, CPU1 may attempt to execute code from unintended memory locations, leading to conflicts with CPU0.

In an AMP configuration, each core typically has its own memory region for code and data. For example, CPU0 might be assigned memory addresses 0x00000000 to 0x1FFFFFFF, while CPU1 is assigned 0x20000000 to 0x3FFFFFFF. If these regions overlap or are not properly configured, CPU1 may access CPU0’s memory, causing unpredictable behavior.

Another potential cause is the lack of a proper bootloader or secondary program loader (SPL) for CPU1. In many AMP systems, CPU0 is responsible for initializing the system and loading the binary for CPU1 into its designated memory region. If this step is skipped or implemented incorrectly, CPU1 may not have valid code to execute, leading to random execution behavior.

Additionally, the ARM Cortex-A9 cores share some resources, such as the L2 cache and interrupt controller. If these resources are not properly partitioned or initialized, they can become points of contention between the cores. For example, if both cores attempt to use the same cache lines or interrupt vectors, it can lead to data corruption or incorrect interrupt handling.

Configuring Core Initialization, Memory Partitioning, and Synchronization

To resolve the issues with AMP baremetal execution on the ARM Cortex-A9 dual-core SoC, a systematic approach is required. This involves configuring core initialization, memory partitioning, and synchronization mechanisms to ensure that each core operates independently and correctly.

Core Initialization

The first step is to ensure that both cores are properly initialized. This involves setting up the reset vector for CPU1 and ensuring that it points to the correct memory location where its binary is loaded. The reset vector for CPU1 can be configured using the following steps:

  1. Set the Reset Vector for CPU1: The reset vector for CPU1 should point to the start address of its binary. This can be done by writing the start address to the appropriate register in the system control block (SCB). For example, if the binary for CPU1 is loaded at 0x20000000, this address should be written to the reset vector register for CPU1.

  2. Release CPU1 from Reset: After setting the reset vector, CPU1 can be released from reset. This is typically done by writing to a control register in the SCB. For example, writing a specific value to the CPU1 reset control register will release CPU1 from reset and start its execution from the reset vector.

  3. Verify CPU1 Execution: Once CPU1 is released from reset, its execution should be verified using a debugger. This involves setting breakpoints at the start of CPU1’s binary and stepping through the code to ensure that it is executing correctly.

Memory Partitioning

Proper memory partitioning is essential to prevent conflicts between the cores. Each core should have its own designated memory region for code and data. The following steps outline how to configure memory partitioning:

  1. Define Memory Regions: Define separate memory regions for CPU0 and CPU1. For example, CPU0 can be assigned memory addresses 0x00000000 to 0x1FFFFFFF, and CPU1 can be assigned 0x20000000 to 0x3FFFFFFF.

  2. Configure Memory Protection Unit (MPU): The MPU can be used to enforce memory partitioning. Each core should have its own MPU configuration that restricts access to its designated memory region. For example, CPU0’s MPU can be configured to allow access only to 0x00000000 to 0x1FFFFFFF, while CPU1’s MPU can be configured to allow access only to 0x20000000 to 0x3FFFFFFF.

  3. Load Binaries into Designated Memory Regions: Ensure that the binaries for CPU0 and CPU1 are loaded into their respective memory regions. This can be done using a bootloader or SPL that loads the binaries from non-volatile storage (e.g., flash memory) into the designated memory regions.

Synchronization Mechanisms

Synchronization mechanisms are necessary to coordinate activities between the cores and prevent conflicts. The following steps outline how to implement synchronization:

  1. Implement Spinlocks: Spinlocks can be used to protect shared resources. For example, if both cores need to access a shared peripheral, a spinlock can be used to ensure that only one core accesses the peripheral at a time. The spinlock can be implemented using atomic operations, such as LDREX and STREX.

  2. Use Mailboxes for Communication: Mailboxes can be used for inter-core communication. Each core can have its own mailbox, and messages can be passed between the cores using these mailboxes. For example, CPU0 can send a message to CPU1’s mailbox to signal that a task is complete.

  3. Configure Interrupts: Interrupts can be used to signal events between the cores. For example, CPU0 can generate an interrupt to signal CPU1 that data is ready in a shared memory region. The interrupt controller should be configured to route the interrupt to the correct core.

Debugging and Verification

Debugging and verification are crucial to ensure that the AMP configuration is working correctly. The following steps outline how to debug and verify the configuration:

  1. Use a Debugger: A debugger can be used to trace the execution flow of both cores. Breakpoints can be set at key points in the code to verify that each core is executing its designated binary.

  2. Monitor Memory Access: Memory access can be monitored using a debugger or logic analyzer to ensure that each core is accessing only its designated memory region.

  3. Check Synchronization Mechanisms: The synchronization mechanisms should be tested to ensure that they are working correctly. For example, spinlocks should be tested to ensure that they prevent concurrent access to shared resources.

  4. Verify Interrupt Handling: Interrupt handling should be verified to ensure that interrupts are routed correctly and handled by the appropriate core.

By following these steps, the issues with AMP baremetal execution on the ARM Cortex-A9 dual-core SoC can be resolved. Proper core initialization, memory partitioning, and synchronization mechanisms are essential to ensure that each core operates independently and correctly. Debugging and verification are crucial to confirm that the configuration is working as expected.

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