Missing CoreSight Components in Renesas R8A77970 Device Tree Source

CoreSight STM and TPIU Driver Integration Failures in R8A77970 SoC

The integration of CoreSight STM (System Trace Macrocell) and TPIU (Trace Port Interface Unit) drivers in the Renesas R8A77970 SoC is encountering significant issues due to missing device tree source (DTS) entries. The absence of critical components such as STM, STM500, ETM4.0, Funnel, Replicator, TMC-ETR, TPIU, TMC-ETF, ETB1.1, and ETBv1.0 in the r8a77970.dtsi file is preventing the proper initialization and operation of these drivers. This results in no kernel logs being printed, which severely hampers debugging and trace functionality.

The CoreSight architecture is a critical component for system trace and debug in ARM-based SoCs. It provides a comprehensive set of tools for tracing and debugging complex systems, including processors, interconnects, and peripherals. The STM is used for system trace, while the TPIU is responsible for exporting trace data to external trace capture devices. The absence of these components in the device tree source means that the kernel is unable to recognize and initialize these hardware blocks, leading to a complete failure in trace functionality.

The device tree source is a critical part of the Linux kernel that describes the hardware components of a system. It is used by the kernel to initialize and configure hardware devices. The r8a77970.dtsi file is expected to contain entries for all the CoreSight components present in the R8A77970 SoC. However, the current version of the file is missing these entries, which is causing the integration issues.

Missing Register Definitions and Clock/Power Domain Information

The absence of register definitions, clock, and power domain information in the r8a77970.dtsi file is a significant barrier to the proper functioning of the CoreSight STM and TPIU drivers. The device tree source is expected to provide the physical base address and length of the register set for each CoreSight component. This information is crucial for the kernel to map the hardware registers into the virtual address space and interact with the hardware.

In addition to the register definitions, the device tree source should also specify the clocks and power domains for each CoreSight component. The clocks are necessary for the proper operation of the hardware, while the power domains are required to manage the power state of the components. The absence of this information in the r8a77970.dtsi file means that the kernel is unable to properly configure and control the CoreSight components.

The Technical Reference Manual (TRM) for the SoC400 and STM components should provide detailed information about the register definitions, clocks, and power domains. However, the user has reported that this information is not available in the TRM. This lack of documentation further complicates the integration process, as it leaves the developer without a reliable source of information to manually add the missing entries to the device tree source.

Implementing CoreSight Device Tree Entries and Driver Configuration

To resolve the issues with the CoreSight STM and TPIU driver integration, the missing device tree entries must be added to the r8a77970.dtsi file. This involves defining the register sets, clocks, and power domains for each CoreSight component. The following steps outline the process of adding these entries and configuring the drivers:

1. Register Definitions: The physical base address and length of the register set for each CoreSight component must be defined in the device tree source. This information can typically be found in the hardware documentation or the TRM. If the TRM does not provide this information, it may be necessary to consult the hardware design team or the silicon vendor for the correct values.

2. Clocks and Power Domains: The clocks and power domains for each CoreSight component must be specified in the device tree source. The clocks are typically provided by the SoC’s clock controller, while the power domains are managed by the power management unit. The device tree source should reference the appropriate clock and power domain nodes for each CoreSight component.

3. Driver Configuration: Once the device tree entries have been added, the CoreSight STM and TPIU drivers must be configured to use these entries. This involves updating the driver code to correctly map the hardware registers, enable the necessary clocks, and manage the power domains. The driver code should also be updated to handle any additional configuration required by the specific CoreSight components in the R8A77970 SoC.

4. Validation and Testing: After adding the device tree entries and configuring the drivers, the system should be validated to ensure that the CoreSight components are properly initialized and functioning. This involves running trace and debug tests to verify that the STM and TPIU are correctly capturing and exporting trace data. Any issues encountered during testing should be debugged and resolved, with further updates to the device tree source and driver code as necessary.

The following table summarizes the required device tree entries for the CoreSight components:

Once the device tree entries have been added, the r8a77970.dtsi file should be updated as follows:

stm: stm@E0100000 {
    compatible = "arm,coresight-stm";
    reg = <0xE0100000 0x1000>;
    clocks = <&clk1>;
    power-domains = <&pd1>;
};

stm500: stm500@E0101000 {
    compatible = "arm,coresight-stm500";
    reg = <0xE0101000 0x1000>;
    clocks = <&clk2>;
    power-domains = <&pd2>;
};

etm4: etm4@E0102000 {
    compatible = "arm,coresight-etm4";
    reg = <0xE0102000 0x1000>;
    clocks = <&clk3>;
    power-domains = <&pd3>;
};

funnel: funnel@E0103000 {
    compatible = "arm,coresight-funnel";
    reg = <0xE0103000 0x1000>;
    clocks = <&clk4>;
    power-domains = <&pd4>;
};

replicator: replicator@E0104000 {
    compatible = "arm,coresight-replicator";
    reg = <0xE0104000 0x1000>;
    clocks = <&clk5>;
    power-domains = <&pd5>;
};

tmc_etr: tmc_etr@E0105000 {
    compatible = "arm,coresight-tmc-etr";
    reg = <0xE0105000 0x1000>;
    clocks = <&clk6>;
    power-domains = <&pd6>;
};

tpiu: tpiu@E0106000 {
    compatible = "arm,coresight-tpiu";
    reg = <0xE0106000 0x1000>;
    clocks = <&clk7>;
    power-domains = <&pd7>;
};

tmc_etf: tmc_etf@E0107000 {
    compatible = "arm,coresight-tmc-etf";
    reg = <0xE0107000 0x1000>;
    clocks = <&clk8>;
    power-domains = <&pd8>;
};

etb11: etb11@E0108000 {
    compatible = "arm,coresight-etb11";
    reg = <0xE0108000 0x1000>;
    clocks = <&clk9>;
    power-domains = <&pd9>;
};

etbv10: etbv10@E0109000 {
    compatible = "arm,coresight-etbv10";
    reg = <0xE0109000 0x1000>;
    clocks = <&clk10>;
    power-domains = <&pd10>;
};

After updating the device tree source, the kernel should be recompiled and deployed to the target system. The system should then be tested to ensure that the CoreSight components are properly initialized and functioning. If any issues are encountered, further debugging and adjustments to the device tree source and driver code may be necessary.

In conclusion, the missing CoreSight components in the r8a77970.dtsi file are causing significant issues with the integration of the STM and TPIU drivers. By adding the necessary device tree entries and configuring the drivers, these issues can be resolved, enabling the proper functioning of the CoreSight trace and debug functionality in the R8A77970 SoC.