NIC301 Write Transaction Behavior with 32-bit BusMatrix and 64-bit Slave
The NIC301 interconnect is designed to handle data width conversion between masters and slaves with different data widths. In this scenario, the bus matrix operates at a 32-bit data width, while the slave interface is configured for a 64-bit data width. During write transactions, the NIC301 splits the 64-bit write data from the slave into two 32-bit transactions for the bus matrix. This is reflected in the behavior of the write strobe signals (wstrb_slave[7:0]), where the high half (wstrb_slave[7:4]) and low half (wstrb_slave[3:0]) toggle interleavedly. This behavior is expected because the NIC301 must handle the 64-bit write data in two 32-bit chunks to match the bus matrix’s data width.
The NIC301 achieves this by generating two separate write transactions for the bus matrix. The first transaction transfers the lower 32 bits of the 64-bit data, and the second transaction transfers the upper 32 bits. The interleaved toggling of the write strobe signals ensures that the correct byte lanes are activated for each 32-bit transaction. This mechanism allows the NIC301 to maintain data integrity and ensure that the write operation is completed correctly.
However, the write transaction behavior also highlights a potential issue with the NIC301’s configuration. If the NIC301 is not properly configured to handle the data width mismatch, it may fail to split the 64-bit write data into two 32-bit transactions. This could result in data corruption or incomplete write operations. Therefore, it is crucial to verify that the NIC301 is configured correctly to handle the data width conversion between the 32-bit bus matrix and the 64-bit slave.
NIC301 Read Transaction Bypass and Timing Mismatch
During read transactions, the NIC301 appears to bypass the data width conversion process and directly transfers the 64-bit read data from the slave to the 32-bit bus matrix. This behavior is unexpected because the NIC301 should split the 64-bit read data into two 32-bit transactions, similar to the write transaction behavior. Instead, the NIC301 transfers the entire 64-bit read data in a single transaction, which results in a timing mismatch between the slave and the bus matrix.
The timing mismatch occurs because the NIC301 does not account for the data width difference between the slave and the bus matrix. The rvalid signal, which indicates that the read data is valid, is asserted for the entire duration of the 64-bit read data transfer. However, the bus matrix expects the rvalid signal to be asserted for only 32 bits of data at a time. As a result, the rvalid signal remains asserted for twice the expected duration, causing a timing mismatch between the slave and the bus matrix.
This behavior suggests that the NIC301 is not properly configured to handle the data width conversion during read transactions. The NIC301 should split the 64-bit read data into two 32-bit transactions and assert the rvalid signal for each transaction separately. This would ensure that the timing of the rvalid signal matches the expectations of the bus matrix and prevents any timing mismatches.
Configuring NIC301 for Correct Data Width Conversion and Timing
To resolve the data width mismatch and timing issues, the NIC301 must be properly configured to handle the data width conversion between the 32-bit bus matrix and the 64-bit slave. This involves setting the appropriate configuration parameters in the NIC301 to ensure that it splits the 64-bit data into two 32-bit transactions during both write and read operations.
For write transactions, the NIC301 should be configured to split the 64-bit write data into two 32-bit transactions and generate the corresponding write strobe signals (wstrb_slave[7:0]) in an interleaved manner. This ensures that the correct byte lanes are activated for each 32-bit transaction and that the write operation is completed correctly.
For read transactions, the NIC301 should be configured to split the 64-bit read data into two 32-bit transactions and assert the rvalid signal for each transaction separately. This ensures that the timing of the rvalid signal matches the expectations of the bus matrix and prevents any timing mismatches.
Additionally, the NIC301’s configuration file should be reviewed to ensure that all parameters related to data width conversion and timing are set correctly. This includes verifying that the data width parameters for the bus matrix and the slave are configured correctly and that the NIC301 is set to handle the data width conversion automatically.
If the NIC301 is still not functioning as expected after verifying the configuration, it may be necessary to contact ARM support for further assistance. The ARM support team can provide additional guidance on configuring the NIC301 and resolving any issues related to data width conversion and timing.
In conclusion, the NIC301 must be properly configured to handle the data width conversion between the 32-bit bus matrix and the 64-bit slave. This involves setting the appropriate configuration parameters to ensure that the NIC301 splits the 64-bit data into two 32-bit transactions during both write and read operations. By doing so, the NIC301 can maintain data integrity and ensure that the timing of the rvalid signal matches the expectations of the bus matrix.
