ARM Cortex-A53 Executable Text Section Size Discrepancy
When compiling a Xilinx hello world application for the ARM Cortex-A53 processor using ARMCC 6.7, the text section size of the resulting executable is significantly larger (~82 KB) compared to the same application compiled with GCC 7.3.1 (~30 KB). This discrepancy is observed despite both compilers using similar optimization levels (-O0) and debug information (-g3). The application is built with a static library (libxil.a) containing peripheral drivers, which is compiled with -O2 optimization for both toolchains. The issue raises concerns about the efficiency of the ARMCC 6.7 compiler in generating compact code for the Cortex-A53 architecture, especially when compared to GCC 7.3.1.
The text section size is a critical metric in embedded systems, as it directly impacts the memory footprint of the application. In resource-constrained environments, such as those using Cortex-A53 processors, minimizing the text section size is essential for efficient memory utilization. The observed discrepancy suggests that ARMCC 6.7 may be introducing additional overhead or failing to optimize certain aspects of the code generation process, leading to an inflated text section size.
Compiler Behavior Differences and Unused Section Retention
One of the primary reasons for the discrepancy in text section size between ARMCC 6.7 and GCC 7.3.1 lies in how each compiler handles unused sections and linker optimizations. GCC is known for its aggressive dead code elimination and section removal during the linking phase, which can significantly reduce the size of the final executable. In contrast, ARMCC 6.7 may retain unused sections, leading to a larger text section size.
The ARMCC 6.7 compiler, by default, may not perform the same level of dead code elimination as GCC 7.3.1. This behavior is particularly evident when linking against static libraries, where unused functions and data sections from the library may not be removed. The result is an executable that includes code and data that are never referenced during the application’s execution, contributing to the increased text section size.
Additionally, the ARMCC 6.7 linker may not apply the same level of section merging and optimization as the GCC linker. Section merging is a technique where similar sections (e.g., read-only data, executable code) are combined to reduce fragmentation and overhead. The lack of such optimizations in ARMCC 6.7 can lead to a less efficient layout of the text section, further increasing its size.
Optimizing Text Section Size with ARMCC 6.7
To address the excessive text section size when using ARMCC 6.7, several steps can be taken to optimize the compilation and linking process. These steps focus on reducing the size of the text section by enabling compiler and linker optimizations, removing unused code, and ensuring efficient section placement.
First, enabling higher optimization levels during compilation can help reduce the text section size. While the original compilation used -O0 (no optimization), switching to -O2 or -Os (optimize for size) can significantly reduce the size of the generated code. The -Os option is particularly effective, as it prioritizes code size reduction over performance improvements.
Second, enabling linker optimizations can help remove unused sections and reduce the overall size of the executable. The ARMCC 6.7 linker supports several options for dead code elimination and section removal. The –remove option can be used to explicitly remove unused sections, while the –inline option can enable function inlining, reducing the overhead of function calls.
Third, reviewing the linker script and scatter file can help identify opportunities for optimizing section placement. Ensuring that sections are aligned efficiently and that unnecessary padding is minimized can reduce the overall size of the text section. Additionally, merging similar sections and removing redundant sections can further optimize the memory layout.
Finally, analyzing the map file generated by the linker can provide insights into the composition of the text section. The map file lists all sections included in the executable, along with their sizes and addresses. By examining the map file, it is possible to identify large sections or functions that contribute significantly to the text section size. Once identified, these sections can be targeted for optimization or removal.
In conclusion, the discrepancy in text section size between ARMCC 6.7 and GCC 7.3.1 for the Cortex-A53 processor is primarily due to differences in compiler and linker behavior. By enabling optimizations, removing unused sections, and optimizing the linker script, it is possible to reduce the text section size when using ARMCC 6.7, bringing it closer to the size achieved with GCC 7.3.1. These steps are essential for ensuring efficient memory utilization in resource-constrained embedded systems.
