AXI 4 Upsizer/Downsizer Protocol Checker Error with WSTRB Alignment

AXI 4 Upsizer/Downsizer WSTRB Misalignment During 256-bit to 128-bit Data Width Conversion

The core issue revolves around a protocol checker error flagged during the conversion of a 256-bit AXI transaction into two 128-bit transactions targeting two separate slaves. The error message, "Write strobes must only be asserted for the correct byte lanes as determined from start address, transfer size, and beat number," indicates a misalignment in the WSTRB signals when the 256-bit transaction is split into two 128-bit transactions. The master initiates a 256-bit transaction with a data width of 256 bits (WDATA[255:0]) and a corresponding WSTRB[31:0]. The module splits this into two 128-bit transactions: WDATA[255:128] and WSTRB[31:16] are routed to Slave 1, while WDATA[127:0] and WSTRB[15:0] are routed to Slave 2. However, the protocol checker for the slaves reports errors, suggesting that the WSTRB signals are not aligned with the expected byte lanes based on the start address (AWADDR), transfer size (AWSIZE), and burst length (AWLEN).

The problem arises because the 256-bit transaction’s start address and address increment logic do not directly translate to the 128-bit slaves. The 256-bit master’s AWADDR, AWSIZE, and AWLEN values are designed for a 256-bit data bus, and splitting this into two 128-bit transactions requires careful adjustment of these signals to ensure that the WSTRB values align with the correct byte lanes for each slave. Without proper address and control signal modification, the WSTRB signals for the 128-bit slaves will not correspond to the intended byte lanes, leading to protocol violations.

Incorrect AWADDR and WSTRB Mapping for 128-bit Slaves During Data Width Conversion

The root cause of the protocol checker error lies in the incorrect handling of the AWADDR, AWSIZE, and AWLEN signals when splitting the 256-bit transaction into two 128-bit transactions. The 256-bit master’s AWADDR specifies the starting address for the 256-bit transaction, and this address increments based on the AWSIZE and AWLEN values for each beat of the burst. When the transaction is split into two 128-bit transactions, the AWADDR for Slave 1 (handling WDATA[255:128]) must be incremented by 16 bytes (128 bits) relative to the original AWADDR to correctly address the upper half of the 256-bit data bus. Similarly, the AWADDR for Slave 2 (handling WDATA[127:0]) must retain the original AWADDR but ensure that the WSTRB signals align with the lower 128 bits.

Additionally, the AWSIZE and AWLEN values for the 128-bit slaves must be adjusted to reflect the narrower data bus width. The AWSIZE for the 128-bit slaves should be set to 128 bits (AWSIZE = 4), and the AWLEN should be doubled to account for the fact that each 256-bit beat from the master corresponds to two 128-bit beats for the slaves. However, this adjustment introduces complexity in managing the WSTRB signals, as the WSTRB values for the second beat of each 128-bit transaction must be set to zero to indicate that no data is being written for that beat. This is because the data for that beat was written to the other 128-bit slave.

For example, consider a 256-bit master transaction with AWADDR = 0x00, AWSIZE = 5 (256 bits), and AWLEN = 3 (4-beat burst). The master writes the following data:

• Beat 1: WDATA[255:0] = {2, 1}, AWADDR = 0x00
• Beat 2: WDATA[255:0] = {4, 3}, AWADDR = 0x20
• Beat 3: WDATA[255:0] = {6, 5}, AWADDR = 0x40
• Beat 4: WDATA[255:0] = {8, 7}, AWADDR = 0x60

When this transaction is split into two 128-bit transactions, the AWADDR for Slave 1 must be incremented by 16 bytes for each beat, while the AWADDR for Slave 2 remains aligned with the original address. The WSTRB signals must also be adjusted to ensure that they correspond to the correct byte lanes for each slave. If this adjustment is not made, the protocol checker will flag errors due to misaligned WSTRB signals.

Correcting AWADDR, AWSIZE, and WSTRB Alignment for 128-bit Slaves

To resolve the protocol checker error, the following steps must be taken to ensure proper alignment of the AWADDR, AWSIZE, and WSTRB signals for the 128-bit slaves:

1. Adjust AWADDR for Slave 1: The AWADDR for Slave 1 must be incremented by 16 bytes (128 bits) relative to the original AWADDR to correctly address the upper half of the 256-bit data bus. For example, if the original AWADDR is 0x00, the AWADDR for Slave 1 should be 0x10 for the first beat, 0x30 for the second beat, and so on.

2. Retain AWADDR for Slave 2: The AWADDR for Slave 2 should retain the original AWADDR but ensure that the WSTRB signals align with the lower 128 bits. For example, if the original AWADDR is 0x00, the AWADDR for Slave 2 should remain 0x00 for the first beat, 0x20 for the second beat, and so on.

3. Set AWSIZE to 128 bits: The AWSIZE for both slaves should be set to 128 bits (AWSIZE = 4) to reflect the narrower data bus width.

4. Double AWLEN for 128-bit Slaves: The AWLEN for the 128-bit slaves should be doubled to account for the fact that each 256-bit beat from the master corresponds to two 128-bit beats for the slaves. For example, if the original AWLEN is 3 (4-beat burst), the AWLEN for the 128-bit slaves should be 7 (8-beat burst).

5. Adjust WSTRB Signals: The WSTRB signals for the 128-bit slaves must be adjusted to ensure that they correspond to the correct byte lanes for each slave. For Slave 1, the WSTRB[31:16] signals should be used, while for Slave 2, the WSTRB[15:0] signals should be used. Additionally, the WSTRB signals for the second beat of each 128-bit transaction must be set to zero to indicate that no data is being written for that beat.

6. Handle Unaligned Start Addresses: If the original AWADDR is unaligned (i.e., not a multiple of 32 bytes), additional complexity is introduced. In this case, the AWADDR for Slave 1 must be incremented by the appropriate offset to correctly address the upper half of the 256-bit data bus, while the AWADDR for Slave 2 must be adjusted to account for the unaligned start address.

By following these steps, the protocol checker error can be resolved, and the 256-bit to 128-bit data width conversion can be implemented correctly. Below is a table summarizing the adjustments required for the AWADDR, AWSIZE, AWLEN, and WSTRB signals:

By carefully adjusting these signals, the 256-bit to 128-bit data width conversion can be implemented without protocol violations, ensuring that the WSTRB signals align with the correct byte lanes for each slave.