ARM PL081 DMA Controller Transfer Limitation to 256 Bytes per Burst
The issue revolves around the ARM PL081 DMA controller’s inability to transfer the full 16KB of data from a custom peripheral to a memory buffer. The DMA controller is configured to transfer data in bursts of 256 bytes, but the transfer stops after completing only the first burst. This behavior is evident from the runtime logs, which show that the DMA controller prepares a transaction of 4080 bytes initially but only transfers 256 bytes. The remaining data is not transferred, leading to incomplete data in the destination buffer.
The DMA controller is configured with a source address width of 4 bytes and a maximum burst size of 256 bytes. The scatter-gather (SG) list is correctly set up with multiple entries, each representing a portion of the 16KB data. However, the DMA controller does not proceed beyond the first burst, indicating a potential issue with the configuration or the DMA controller’s internal logic.
The runtime logs reveal that the DMA controller prepares multiple Linked List Items (LLIs) for the transfer, each corresponding to a portion of the 16KB data. However, the transfer stops after the first LLI, which corresponds to the initial 4080 bytes. This suggests that the DMA controller is not correctly chaining the LLIs or is encountering an error during the transfer process.
Incorrect DMA Configuration and LLI Chaining Issues
The root cause of the issue lies in the configuration of the DMA controller and the way the Linked List Items (LLIs) are chained. The DMA controller is configured with a maximum burst size of 256 bytes, which is correct for the peripheral’s requirements. However, the issue arises from the way the LLIs are set up and chained. The DMA controller is expected to chain multiple LLIs to transfer the full 16KB of data, but it fails to do so.
The first LLI is correctly set up with a size of 4080 bytes, but the subsequent LLIs are not being processed. This could be due to an incorrect configuration of the DMA controller’s control registers or an issue with the way the LLIs are linked. The DMA controller’s control registers must be configured to enable chaining of LLIs, and each LLI must correctly point to the next LLI in the chain.
Another potential cause is the DMA controller’s internal state machine, which may be getting stuck after processing the first LLI. This could be due to a bug in the DMA controller’s firmware or an issue with the way the DMA controller handles interrupts. The DMA controller is expected to generate an interrupt after completing each LLI, but if the interrupt is not generated or not handled correctly, the DMA controller may not proceed to the next LLI.
The runtime logs show that the DMA controller allocates a physical channel for the transfer and sets up the first LLI correctly. However, the logs do not show any evidence of the DMA controller processing the subsequent LLIs. This suggests that the DMA controller is either not correctly chaining the LLIs or is encountering an error during the transfer process.
Implementing Correct DMA Configuration and Debugging LLI Chaining
To resolve the issue, the DMA controller’s configuration must be reviewed and corrected. The first step is to ensure that the DMA controller’s control registers are correctly configured to enable chaining of LLIs. The control registers must be set to enable the DMA controller to process multiple LLIs in sequence. This includes setting the correct values for the source and destination addresses, the transfer size, and the control bits that enable chaining.
The next step is to verify the setup of the LLIs. Each LLI must correctly point to the next LLI in the chain, and the control bits in each LLI must be set to enable the DMA controller to proceed to the next LLI. The runtime logs show that the LLIs are correctly set up with the correct source and destination addresses and transfer sizes. However, the logs do not show any evidence of the DMA controller processing the subsequent LLIs. This suggests that the issue may be with the way the LLIs are linked or with the DMA controller’s internal logic.
To debug the issue, the DMA controller’s internal state machine must be examined. This can be done by adding debug statements to the DMA controller’s firmware to track the state of the state machine and the processing of each LLI. The debug statements should be added at key points in the state machine, such as when an LLI is processed, when an interrupt is generated, and when the state machine transitions to the next state.
If the issue is with the DMA controller’s firmware, the firmware must be updated to correctly handle the chaining of LLIs. This may involve modifying the state machine to ensure that it correctly processes each LLI and transitions to the next LLI in the chain. The firmware must also be updated to correctly handle interrupts and ensure that the DMA controller proceeds to the next LLI after completing the current one.
If the issue is with the way the LLIs are linked, the setup of the LLIs must be reviewed and corrected. Each LLI must correctly point to the next LLI in the chain, and the control bits in each LLI must be set to enable the DMA controller to proceed to the next LLI. The runtime logs show that the LLIs are correctly set up with the correct source and destination addresses and transfer sizes. However, the logs do not show any evidence of the DMA controller processing the subsequent LLIs. This suggests that the issue may be with the way the LLIs are linked or with the DMA controller’s internal logic.
In conclusion, the issue with the ARM PL081 DMA controller’s inability to transfer the full 16KB of data from a custom peripheral to a memory buffer is likely due to an incorrect configuration of the DMA controller’s control registers or an issue with the way the LLIs are chained. To resolve the issue, the DMA controller’s configuration must be reviewed and corrected, and the setup of the LLIs must be verified. Additionally, the DMA controller’s internal state machine must be examined to ensure that it correctly processes each LLI and transitions to the next LLI in the chain.
