ARM Cortex-A53 System Control Register Access Errors in AArch64 and AArch32 Modes
The ARM Cortex-A53 processor, a popular choice for embedded systems, supports both AArch64 (64-bit) and AArch32 (32-bit) execution states. Accessing system control registers, such as the System Control Register (SCTLR), is a common task for low-level firmware development. However, developers often encounter errors when attempting to access these registers, particularly when transitioning between AArch64 and AArch32 modes. This post delves into the specific issues related to accessing the SCTLR in both modes, the underlying causes, and the steps required to resolve these issues.
Compilation and Runtime Errors When Accessing SCTLR_EL1 and SCTLR in AArch64 and AArch32 Modes
When attempting to access the System Control Register (SCTLR) in an ARM Cortex-A53 processor, developers may encounter two primary types of errors: compilation errors and runtime errors. These errors are often tied to the execution state (AArch64 or AArch32) and the specific instructions used to access the register.
In AArch64 mode, the SCTLR is accessed using the SCTLR_EL1 register. The following code snippet demonstrates an attempt to read the SCTLR_EL1 register in AArch64 mode:
#include <stdio.h>
unsigned int A_bit() {
unsigned int res = 0;
__asm volatile (
"MRS %[result], SCTLR_EL1": [result] "=r" (res)
);
return res;
}
int main(void) {
unsigned int sys_reg = 0;
sys_reg = A_bit();
printf("system register value is %d\n", sys_reg);
}
During compilation, the following error may occur:
/tmp/cc7Dc236.s: Assembler messages:
/tmp/cc7Dc236.s:31: Error: selected processor does not support requested special purpose register -- `mrs r3,SCTLR_EL1'
This error indicates that the compiler is not generating code for the AArch64 execution state. Instead, it is attempting to compile the code for AArch32, where the SCTLR_EL1 register is not recognized.
In AArch32 mode, the SCTLR is accessed using the MRC instruction, as shown in the following code snippet:
#include <stdio.h>
unsigned int A_bit() {
unsigned int res = 0;
__asm volatile (
"MRC p15, 0, %[result], c1, c0, 0": [result] "=r" (res)
);
return res;
}
int main(void) {
unsigned int sys_reg = 0;
sys_reg = A_bit();
printf("system register value is %d\n", sys_reg);
}
While this code compiles successfully, it may result in a runtime error:
Illegal instruction
This error occurs because the MRC instruction is attempting to access the SCTLR from an exception level (EL0) that does not have the necessary privileges to read the register.
Misconfigured Compiler Flags and Privilege Level Mismatches
The root causes of these errors can be traced to two primary issues: misconfigured compiler flags and privilege level mismatches.
Misconfigured Compiler Flags: The ARM Cortex-A53 processor supports both AArch64 and AArch32 execution states. When compiling code for the Cortex-A53, it is essential to specify the correct execution state using the appropriate compiler flags. For example, when compiling for AArch64, the -march=armv8-a flag should be used to ensure that the compiler generates code for the AArch64 execution state. Failure to specify the correct execution state can result in the compiler generating code for the wrong architecture, leading to errors such as the one encountered when attempting to access SCTLR_EL1.
Privilege Level Mismatches: The ARM architecture defines several exception levels (EL0, EL1, EL2, and EL3), each with different privileges. The SCTLR is a privileged register that can only be accessed from EL1 or higher. Attempting to access the SCTLR from EL0 (user mode) will result in an "Illegal instruction" error. This is because the MRC instruction used to access the SCTLR in AArch32 mode is privileged and cannot be executed from EL0.
Configuring Compiler Flags and Ensuring Correct Privilege Levels for SCTLR Access
To resolve the issues related to accessing the SCTLR in both AArch64 and AArch32 modes, developers must take the following steps:
1. Configuring Compiler Flags for AArch64 and AArch32 Modes:
When compiling code for the ARM Cortex-A53, it is crucial to specify the correct execution state using the appropriate compiler flags. For AArch64 mode, the following flags should be used:
gcc -march=armv8-a -o aarch64_program aarch64_program.c
For AArch32 mode, the following flags should be used:
gcc -march=armv7-a -mfpu=vfpv3 -mfloat-abi=hard -o aarch32_program aarch32_program.c
These flags ensure that the compiler generates code for the correct execution state, preventing errors related to unsupported special-purpose registers.
2. Ensuring Correct Privilege Levels for SCTLR Access:
To access the SCTLR from EL1 or higher, developers must ensure that the code is executed in the correct privilege level. This can be achieved by running the code in a privileged context, such as an operating system kernel or a bare-metal firmware environment. If the code must be executed from EL0, developers can use a system call (SVC) to transition to EL1, where the SCTLR can be accessed.
For example, in AArch64 mode, the following code demonstrates how to access the SCTLR_EL1 register from EL1:
#include <stdio.h>
unsigned int A_bit() {
unsigned int res = 0;
__asm volatile (
"MRS %[result], SCTLR_EL1": [result] "=r" (res)
);
return res;
}
int main(void) {
unsigned int sys_reg = 0;
// Transition to EL1 (requires privileged context)
__asm volatile (
"SVC #0"
);
sys_reg = A_bit();
printf("system register value is %d\n", sys_reg);
}
In AArch32 mode, the following code demonstrates how to access the SCTLR from EL1:
#include <stdio.h>
unsigned int A_bit() {
unsigned int res = 0;
__asm volatile (
"MRC p15, 0, %[result], c1, c0, 0": [result] "=r" (res)
);
return res;
}
int main(void) {
unsigned int sys_reg = 0;
// Transition to EL1 (requires privileged context)
__asm volatile (
"SVC #0"
);
sys_reg = A_bit();
printf("system register value is %d\n", sys_reg);
}
3. Using ARMv8-A Reference Manual for Guidance:
The ARMv8-A Reference Manual is an invaluable resource for understanding the architecture and the specific requirements for accessing system registers. Developers should consult the manual to ensure that they are using the correct instructions and privilege levels when accessing the SCTLR. The manual provides detailed information on the SCTLR and other system registers, including their accessibility from different exception levels.
4. Debugging and Testing:
Finally, developers should thoroughly test their code to ensure that it behaves as expected in both AArch64 and AArch32 modes. This includes verifying that the correct compiler flags are used, that the code is executed in the correct privilege level, and that the SCTLR is accessed correctly. Debugging tools such as GDB can be used to step through the code and verify that the correct registers are being accessed.
By following these steps, developers can successfully access the SCTLR in both AArch64 and AArch32 modes on the ARM Cortex-A53 processor, avoiding the common pitfalls associated with misconfigured compiler flags and privilege level mismatches.
