APB Write Transactions with PSTRB = “0000” or “0101”: Behavior and Compliance

APB Write Transaction Behavior with PSTRB = "0000"

The Advanced Peripheral Bus (APB) protocol, part of the ARM AMBA (Advanced Microcontroller Bus Architecture) family, is designed for low-power, low-complexity peripheral interfacing. One of the key signals in APB write transactions is the PSTRB (Peripheral Strobe) signal, which indicates the validity of each byte lane during a write operation. When PSTRB is set to "0000" during a write transaction, it implies that none of the byte lanes are valid, and thus, no data should be written to the target peripheral.

In a typical APB write transaction, the PSTRB signal is used to mask the data being written. Each bit in the PSTRB signal corresponds to a byte lane in the data bus. For example, in a 32-bit data bus, PSTRB would be a 4-bit signal, with each bit representing one byte lane. When a bit in PSTRB is set to ‘1’, the corresponding byte lane is valid, and the data on that lane should be written to the peripheral. Conversely, when a bit is ‘0’, the corresponding byte lane is invalid, and the data on that lane should be ignored.

When PSTRB is "0000", all byte lanes are invalid, and the peripheral should not update its registers with the data on the bus. However, the transaction itself is still valid, and the peripheral should acknowledge the transaction by asserting the PREADY signal. This behavior is crucial for maintaining protocol compliance and ensuring that the bus remains in a known state.

The key point here is that the PSTRB signal does not affect the validity of the transaction itself; it only affects the data being written. The transaction will still complete, and the peripheral will still acknowledge it, but no data will be written. This behavior is consistent with the APB protocol specification, which allows for partial writes and non-contiguous byte lane updates.

Potential Misinterpretations and Compliance Issues with PSTRB = "0101"

The PSTRB signal can also take on non-contiguous values, such as "0101" or "1010", which indicate that only certain byte lanes are valid. For example, a PSTRB value of "0101" would indicate that the first and third byte lanes are valid, while the second and fourth are not. This allows for more granular control over which parts of the data bus are updated during a write transaction.

However, the use of non-contiguous PSTRB values can lead to potential misinterpretations and compliance issues, especially if the peripheral or the bus fabric is not designed to handle such cases. For instance, some peripherals may assume that PSTRB will always be contiguous (e.g., "1111" or "0000") and may not correctly handle cases where only certain byte lanes are valid. This can lead to incorrect data being written or read, or even protocol violations.

Another potential issue arises when the PSTRB signal is not driven correctly during read transactions. According to the APB protocol, PSTRB should be driven low ("0000") during read transactions, as it is only relevant for write operations. However, if PSTRB is not driven low during a read transaction, it could lead to unexpected behavior, especially if the peripheral or bus fabric interprets the PSTRB signal during reads. This could result in data corruption or protocol violations.

The APB protocol does not explicitly forbid the use of non-contiguous PSTRB values, but it does require that peripherals and bus fabrics handle all possible PSTRB values correctly. This includes cases where PSTRB is "0000" or non-contiguous values like "0101". Failure to handle these cases correctly can lead to compliance issues and potential bugs in the system.

Correct Handling of PSTRB in APB Write and Read Transactions

To ensure correct handling of the PSTRB signal in APB write and read transactions, designers must follow a set of best practices and guidelines. These include:

1. Properly Handling PSTRB = "0000" During Write Transactions: When PSTRB is "0000" during a write transaction, the peripheral should not update its registers with the data on the bus. However, the transaction should still be acknowledged by asserting the PREADY signal. This ensures that the bus remains in a known state and that the transaction completes successfully, even though no data is written.

2. Supporting Non-Contiguous PSTRB Values: Peripherals and bus fabrics must be designed to handle all possible PSTRB values, including non-contiguous values like "0101" or "1010". This means that the peripheral should only update the byte lanes that are indicated as valid by the PSTRB signal and leave the other byte lanes unchanged. This requires careful design of the data path and control logic within the peripheral.

3. Driving PSTRB Low During Read Transactions: During read transactions, the PSTRB signal should always be driven low ("0000") by the master. This is because PSTRB is only relevant for write operations, and driving it low during reads ensures that the peripheral does not misinterpret the signal. If the master fails to drive PSTRB low during a read transaction, it could lead to unexpected behavior, such as data corruption or protocol violations.

4. Verification of PSTRB Handling: To ensure that the PSTRB signal is handled correctly in all cases, thorough verification is required. This includes testing all possible PSTRB values during write transactions, as well as ensuring that PSTRB is driven low during read transactions. Verification should also include corner cases, such as back-to-back transactions with different PSTRB values, to ensure that the peripheral and bus fabric handle these cases correctly.

5. Documentation and Compliance: Finally, it is important to document the handling of the PSTRB signal in the design specification and ensure that the design complies with the APB protocol. This includes specifying how the peripheral handles PSTRB values of "0000" and non-contiguous values, as well as ensuring that the master drives PSTRB low during read transactions. Compliance with the APB protocol is essential for ensuring interoperability with other components in the system.

By following these guidelines, designers can ensure that the PSTRB signal is handled correctly in APB write and read transactions, avoiding potential issues and ensuring compliance with the APB protocol. This is particularly important in complex SoC designs, where multiple peripherals and bus fabrics may be involved, and where incorrect handling of the PSTRB signal could lead to system-level issues.

Conclusion

The PSTRB signal plays a critical role in APB write transactions, allowing for granular control over which byte lanes are updated during a write operation. However, its behavior can be complex, especially when dealing with non-contiguous values like "0101" or when PSTRB is "0000" during a write transaction. Designers must ensure that their peripherals and bus fabrics handle all possible PSTRB values correctly, and that PSTRB is driven low during read transactions to avoid protocol violations.

Thorough verification is essential to ensure that the PSTRB signal is handled correctly in all cases, and documentation should clearly specify how the signal is handled in the design. By following these best practices, designers can ensure compliance with the APB protocol and avoid potential issues in their SoC designs.