TrustZone Memory Partitioning and Configuration on Cortex-A57
The ARM Cortex-A57 processor, part of the ARMv8-A architecture, incorporates ARM TrustZone technology to provide a secure execution environment alongside the normal world. TrustZone divides the system into two worlds: the Secure World (for trusted applications and firmware) and the Normal World (for general-purpose operating systems and applications). Memory partitioning between these worlds is a critical aspect of system design, as it ensures isolation and security while enabling controlled interaction.
The Cortex-A57 does not inherently define fixed memory regions for Secure and Normal Worlds. Instead, memory partitioning is programmable and typically configured during boot time by the ARM Trusted Firmware (ATF) or the bootloader. The configuration involves setting up the Memory Protection Unit (MPU) or Memory Management Unit (MMU) to define which memory regions are accessible to the Secure World, the Normal World, or both. This is achieved through page table entries and specific hardware registers.
The Secure World can access both secure and non-secure memory, while the Normal World is restricted to non-secure memory unless explicitly granted access. The partitioning is controlled by the Non-Secure (NS) bit in the page table entries. When the NS bit is set to 0, the memory region is secure and accessible only to the Secure World. When the NS bit is set to 1, the memory region is non-secure and accessible to both worlds, provided the appropriate permissions are set.
The bootloader or firmware determines the total available RAM in the system by querying the hardware or relying on predefined memory maps. This information is then used to configure the memory regions for Secure and Normal Worlds. The configuration is often SoC-specific, as the memory controller and TrustZone implementation details vary between vendors. For example, the NVIDIA Tegra X2 (used in the Jetson TX2 development board) has its own memory partitioning mechanisms, which are documented in the SoC-specific technical reference manual (TRM).
Memory Partitioning Mechanisms and NS Bit Configuration
The memory partitioning between Secure and Normal Worlds is governed by the ARMv8-A MMU architecture and the TrustZone security extensions. The key mechanism for controlling memory access is the Non-Secure (NS) bit in the page table entries. This bit determines whether a memory region is secure or non-secure. Additionally, the Shareability attribute in the page table entries controls whether a memory region is shared between worlds or private to one world.
The NS bit is part of the page table descriptor in the ARMv8-A MMU. When the NS bit is set to 0, the corresponding memory region is secure and can only be accessed by the Secure World. When the NS bit is set to 1, the memory region is non-secure and can be accessed by both worlds, provided the appropriate access permissions are configured. The NS bit must be manually set during the initialization of the page tables, typically by the bootloader or firmware.
The Shareability attribute in the page table entries determines whether a memory region is shared between multiple cores or worlds. A memory region marked as "Inner Shareable" can be accessed by multiple cores in the same world, while a region marked as "Outer Shareable" can be accessed by cores in different worlds. For memory regions that need to be shared between Secure and Normal Worlds, the Shareability attribute must be configured appropriately.
In addition to the NS bit and Shareability attribute, the ARMv8-A architecture provides other mechanisms for controlling memory access, such as the Access Permission (AP) bits and the Execute Never (XN) bit. These bits allow fine-grained control over read, write, and execute permissions for each memory region.
The configuration of these attributes is typically done during the initialization of the MMU by the bootloader or firmware. For example, the ARM Trusted Firmware (ATF) provides a set of APIs for configuring the MMU and setting up the memory regions for Secure and Normal Worlds. The configuration is often SoC-specific, as the memory controller and TrustZone implementation details vary between vendors.
Mapping Normal World Memory into Secure World and Troubleshooting Steps
Mapping Normal World memory into the Secure World requires careful configuration of the MMU and page tables. The Secure World can access Normal World memory by setting the NS bit to 1 in the page table entries for the corresponding memory regions. Additionally, the Shareability attribute must be configured to allow access from both worlds.
To map Normal World memory into the Secure World, follow these steps:
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Identify the Memory Region: Determine the physical address range of the Normal World memory region that needs to be accessed by the Secure World. This information is typically provided by the bootloader or firmware.
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Configure the Page Table Entries: Update the page table entries for the identified memory region to set the NS bit to 1. This marks the memory region as non-secure and allows access from both worlds. Additionally, configure the Shareability attribute to "Outer Shareable" to enable sharing between worlds.
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Set Access Permissions: Configure the Access Permission (AP) bits in the page table entries to grant the appropriate read, write, and execute permissions for the Secure World. Ensure that the Execute Never (XN) bit is set appropriately to prevent unauthorized code execution.
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Invalidate the TLB: After updating the page table entries, invalidate the Translation Lookaside Buffer (TLB) to ensure that the changes take effect immediately. This can be done using the
TLBIinstruction in ARMv8-A. -
Verify the Configuration: Test the configuration by accessing the mapped memory region from the Secure World. Use debug tools or logging to verify that the memory access is successful and that the permissions are enforced correctly.
If the Secure World is unable to access the mapped memory region, consider the following troubleshooting steps:
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Check the NS Bit: Verify that the NS bit is set to 1 in the page table entries for the memory region. If the NS bit is set to 0, the memory region is secure and inaccessible from the Normal World.
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Verify Shareability Attribute: Ensure that the Shareability attribute is configured correctly to allow access from both worlds. If the attribute is set to "Non-Shareable," the memory region is private to one world and cannot be accessed from the other.
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Review Access Permissions: Check the Access Permission (AP) bits in the page table entries to ensure that the Secure World has the appropriate read, write, and execute permissions. If the permissions are too restrictive, the Secure World may be unable to access the memory region.
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Inspect TLB Entries: Use debug tools to inspect the TLB entries and verify that the updated page table entries are correctly loaded. If the TLB entries are stale, invalidate the TLB and retry the memory access.
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Consult SoC Documentation: Refer to the SoC-specific technical reference manual (TRM) for additional details on memory partitioning and TrustZone configuration. Some SoCs, such as the NVIDIA Tegra X2, have unique memory partitioning mechanisms that may require special configuration.
By following these steps and troubleshooting guidelines, you can successfully map Normal World memory into the Secure World and ensure secure and efficient interaction between the two worlds.
