ARM Cortex-A9 PMU Initialization and Sampling Issues on Arria10 SoC

ARM Cortex-A9 PMU Hardware and Sampling Capabilities

The Performance Monitoring Unit (PMU) in ARM Cortex-A9 processors is a critical component for profiling and performance analysis. It provides hardware counters to measure events such as cycles, instructions executed, cache misses, and branch predictions. However, the PMU’s functionality is not always straightforward, especially when integrated into System-on-Chip (SoC) designs like the Arria10. The PMU’s ability to generate overflow interrupts and support sampling is essential for tools like Linux’s perf to function correctly. In the case of the Arria10 SoC, the PMU hardware is present, but the lack of sampling or overflow interrupt support indicates a potential issue with either the hardware implementation or the software configuration.

The PMU in Cortex-A9 is accessed via the CP14 interface and is optional in some SoC designs. While the PMU itself is part of the ARM CPU, its integration into the SoC can vary. Specifically, the overflow interrupt mechanism, which is necessary for sampling-based profiling, may not be implemented or properly configured. This is evident when running perf record, which fails with the error: "PMU Hardware doesn’t support sampling/overflow-interrupts." This error suggests that the PMU cannot generate interrupts when counters overflow, a requirement for sampling-based profiling.

To further diagnose the issue, it is essential to verify whether the PMU interrupt is implemented in the SoC. This can be done by checking the /proc/interrupts file for PMU-related entries. If no PMU-related interrupts are listed, it indicates that the PMU interrupt is either not implemented or not configured correctly in the kernel. Additionally, examining the kernel boot logs (dmesg) for PMU initialization messages can provide insights into whether the PMU driver was successfully loaded and configured.

PMU Interrupt Implementation and Kernel Configuration

The absence of PMU interrupt support in the Arria10 SoC is a significant limitation for performance profiling. The PMU interrupt is necessary for tools like perf to capture samples at regular intervals or when specific events occur. Without this interrupt, the PMU can only be used for counting events, not for sampling-based profiling. This limitation is not inherent to the Cortex-A9 architecture but is specific to the Arria10 SoC’s implementation.

The kernel configuration plays a crucial role in enabling PMU support. The Linux kernel must be compiled with the appropriate options to support the PMU and its interrupts. For Cortex-A9, this typically involves enabling options such as CONFIG_HW_PERF_EVENTS, CONFIG_ARM_PMU, and CONFIG_ARM_PMU_ACPI (if applicable). However, even with these options enabled, the PMU may not function correctly if the SoC does not implement the necessary hardware support for PMU interrupts.

In the case of the Arria10 SoC, the mainline Linux kernel does not yet include support for PMU interrupts. However, patches are available in Altera’s custom kernels (e.g., socfpga-4.15 and socfpga-4.16) that add this support. These patches modify the kernel’s Device Tree Source (DTS) files to include PMU interrupt definitions and enable the necessary drivers. Applying these patches may resolve the issue, but it requires rebuilding the kernel with the modified sources.

The Device Tree Source (DTS) is a critical component for configuring hardware in ARM-based systems. It describes the hardware layout, including interrupts, memory maps, and peripheral configurations. For the PMU to function correctly, the DTS must include entries for the PMU interrupt. For example, the Juno SoC’s DTS includes the following PMU configuration:

pmu {
    compatible = "arm,cortex-a72-pmu";
    interrupts = <0x0 0x3 0xf04>;
};

This configuration specifies the PMU’s compatibility with the Cortex-A72 PMU driver and defines the interrupt line. A similar configuration is required for the Cortex-A9 PMU in the Arria10 SoC. Without this configuration, the kernel will not recognize the PMU interrupt, and perf will not be able to use sampling-based profiling.

Implementing PMU Support and Troubleshooting Steps

To enable PMU support on the Arria10 SoC, the following steps should be taken:

1. Verify PMU Hardware Support: Check the SoC’s technical reference manual to confirm that the PMU and its interrupt mechanism are implemented. If the PMU interrupt is not listed, it may not be supported by the hardware.

2. Check Kernel Configuration: Ensure that the Linux kernel is compiled with the necessary options to support the PMU. This includes enabling CONFIG_HW_PERF_EVENTS, CONFIG_ARM_PMU, and any other relevant options.

3. Apply Custom Kernel Patches: If the mainline kernel does not support PMU interrupts for the Arria10 SoC, apply the patches available in Altera’s custom kernels. These patches modify the DTS and enable the PMU interrupt support.

4. Modify Device Tree Source (DTS): Update the DTS to include PMU interrupt definitions. This involves adding entries similar to the Juno SoC’s PMU configuration. Ensure that the interrupt line and compatibility strings match the Cortex-A9 PMU.

5. Rebuild and Test the Kernel: Rebuild the kernel with the modified DTS and applied patches. Boot the new kernel and check the /proc/interrupts file for PMU-related entries. Additionally, examine the dmesg output for PMU initialization messages.

6. Test perf Functionality: Run perf record to verify that sampling-based profiling now works. If the PMU interrupt is correctly configured, perf should be able to capture samples without errors.

If these steps do not resolve the issue, it may be necessary to consult the SoC manufacturer for additional support or consider alternative profiling tools that do not rely on PMU interrupts. In some cases, hardware limitations may prevent the use of sampling-based profiling, and event counting may be the only available option.

In conclusion, the lack of PMU interrupt support in the Arria10 SoC is a significant limitation for performance profiling. However, by carefully verifying the hardware implementation, configuring the kernel, and applying custom patches, it may be possible to enable PMU functionality. The process requires a deep understanding of both the hardware and software components involved, as well as meticulous attention to detail in configuring the kernel and Device Tree Source.