ARM Cortex-M0+ WFI Instruction Ignored During Deep Sleep Mode

ARM Cortex-M0+ WFI Instruction Ignored During Deep Sleep Mode

Issue Overview

The ARM Cortex-M0+ processor, specifically the STM32L051 microcontroller, is occasionally ignoring the Wait For Interrupt (WFI) instruction when attempting to enter deep sleep mode. This issue manifests as the processor failing to enter the low-power state and instead continuing to execute code, which defeats the purpose of power-saving mechanisms. The WFI instruction is a critical part of the ARM architecture, designed to put the processor into a low-power state until an interrupt occurs. When this instruction is ignored, the processor remains active, leading to unnecessary power consumption and potential system instability.

The problem is particularly perplexing because the WFI instruction works correctly most of the time, but under certain conditions, it fails to trigger the expected low-power state. This intermittent behavior suggests that the issue is not a straightforward hardware fault but rather a subtle interaction between the software configuration and the processor’s internal state. The code provided in the discussion shows a sequence of operations intended to prepare the processor for deep sleep, including disabling interrupts, configuring power control registers, and setting the SLEEPDEEP bit in the System Control Block (SCB). Despite these preparations, the WFI instruction is sometimes ignored.

Possible Causes

Several factors could contribute to the Cortex-M0+ processor ignoring the WFI instruction during deep sleep mode. These include pending interrupts, improper configuration of power control registers, and issues with the interrupt masking and pending flag management.

Pending Interrupts: One of the most common reasons for the WFI instruction being ignored is the presence of pending interrupts. The WFI instruction is designed to put the processor into a low-power state until an interrupt occurs. However, if an interrupt is already pending when the WFI instruction is executed, the processor may immediately resume execution instead of entering the low-power state. This behavior is by design, as the processor must service the pending interrupt. In the provided code, the presence of pending interrupts is checked using the NVIC->ICPR[0] register, which indicates that some interrupts were indeed pending in earlier versions of the code.

Improper Configuration of Power Control Registers: The Cortex-M0+ processor relies on several power control registers to manage its low-power states. These include the Power Control Register (PWR->CR) and the Power Control/Status Register (PWR->CSR). If these registers are not configured correctly, the processor may fail to enter the desired low-power state. For example, the PWR_CR_PDDS bit must be set to indicate that the processor should enter standby mode when the WFI instruction is executed. Additionally, the PWR_CR_LPSDSR bit must be set to enable low-power deep sleep mode. If these bits are not set correctly, the processor may ignore the WFI instruction.

Interrupt Masking and Pending Flag Management: The Cortex-M0+ processor uses the Nested Vectored Interrupt Controller (NVIC) to manage interrupts. The NVIC includes several registers that control interrupt masking and pending flags. If these registers are not managed correctly, interrupts may remain pending even after they have been serviced, causing the WFI instruction to be ignored. In the provided code, the EXTI->IMR register is used to mask interrupts, and the EXTI->PR register is used to clear pending interrupt flags. However, if these registers are not managed correctly, interrupts may remain pending, preventing the processor from entering the low-power state.

Troubleshooting Steps, Solutions & Fixes

To resolve the issue of the Cortex-M0+ processor ignoring the WFI instruction during deep sleep mode, several steps can be taken. These include ensuring that all pending interrupts are cleared before executing the WFI instruction, properly configuring the power control registers, and correctly managing the interrupt masking and pending flags.

Clearing Pending Interrupts: Before executing the WFI instruction, it is essential to ensure that all pending interrupts are cleared. This can be done by checking the NVIC->ICPR[0] register and clearing any pending interrupt flags. In the provided code, this is done using the following sequence:

if(NVIC->ICPR[0])
{
    Send_USART("Interrupt!->");
    USART_unr32(NVIC->ICPR[0]);
    USART_send( 0x0D );
    USART_send( 0x0A );
    NVIC->ICPR[0] = 64;
    USART_send( ' ' );
    USART_unr32(NVIC->ICPR[0]);
    USART_send( 0x0D );
    USART_send( 0x0A );
}

This code checks the NVIC->ICPR[0] register for any pending interrupts and clears them if necessary. This ensures that no interrupts are pending when the WFI instruction is executed, allowing the processor to enter the low-power state as expected.

Properly Configuring Power Control Registers: The power control registers must be configured correctly to ensure that the processor enters the desired low-power state when the WFI instruction is executed. This includes setting the PWR_CR_PDDS bit to indicate that the processor should enter standby mode and setting the PWR_CR_LPSDSR bit to enable low-power deep sleep mode. The following code shows how these registers are configured in the provided example:

PWR->CSR |= PWR_CSR_EWUP2;
PWR->CR |= PWR_CR_CWUF | // clear the WUF flag after 2 clock cycles
           PWR_CR_CSBF | // clear StandBy flag
           PWR_CR_ULP;   // V_{REFINT} is off in low-power mode
PWR->CR |= PWR_CR_LPSDSR | //
           PWR_CR_PDDS;  // Enter Standby mode when the CPU enters deepsleep
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; // low-power mode = stop mode

This code sets the necessary bits in the power control registers to ensure that the processor enters the correct low-power state when the WFI instruction is executed.

Managing Interrupt Masking and Pending Flags: The NVIC registers must be managed correctly to ensure that interrupts are properly masked and pending flags are cleared. This includes using the EXTI->IMR register to mask interrupts and the EXTI->PR register to clear pending interrupt flags. The following code shows how these registers are managed in the provided example:

EXTI->IMR = 0; // clear all interrupt mask
NVIC_DisableIRQ( EXTI2_3_IRQn ); // disable interrupt from INT pin
EXTI->PR |= EXTI_PR_PIF2; // clear interrupt pending flag
__disable_irq();

This code ensures that all interrupts are masked and any pending interrupt flags are cleared before the WFI instruction is executed. This prevents any pending interrupts from causing the processor to ignore the WFI instruction.

Additional Considerations: In addition to the above steps, it is also important to ensure that the processor is in a stable state before executing the WFI instruction. This includes ensuring that all necessary peripherals are properly configured and that any pending operations are completed. It may also be necessary to add additional debugging code to monitor the state of the processor and identify any potential issues that could cause the WFI instruction to be ignored.

By following these steps, the issue of the Cortex-M0+ processor ignoring the WFI instruction during deep sleep mode can be resolved. This ensures that the processor enters the desired low-power state, reducing power consumption and improving system stability.

Summary of Key Points

Issue	Description	Solution
Pending Interrupts	Interrupts that are pending when WFI is executed can prevent the processor from entering low-power mode.	Clear all pending interrupts using NVIC->ICPR[0] before executing WFI.
Power Control Register Configuration	Incorrect configuration of power control registers can prevent the processor from entering low-power mode.	Ensure PWR_CR_PDDS and PWR_CR_LPSDSR bits are set correctly.
Interrupt Masking and Pending Flags	Improper management of interrupt masking and pending flags can cause interrupts to remain pending.	Use EXTI->IMR to mask interrupts and EXTI->PR to clear pending flags.
Processor State Stability	The processor must be in a stable state before executing WFI to ensure proper low-power mode entry.	Ensure all peripherals are configured and pending operations are completed.

By addressing these key points, the issue of the Cortex-M0+ processor ignoring the WFI instruction during deep sleep mode can be effectively resolved, ensuring reliable low-power operation.