ARMv7-A8 Secure Monitor Mode Transition and Secure Configuration Register Access Issues

ARM Cortex-A8 Secure Monitor Mode Transition Challenges

The ARM Cortex-A8 processor, as implemented in the TI AM3358 Sitara SoC, provides a secure execution environment through the Secure Monitor Mode (SMM). This mode acts as a gateway between the normal world (non-secure state) and the secure world (secure state). The transition to Secure Monitor Mode is typically initiated through the Secure Monitor Call (SMC) instruction, which generates a secure monitor exception. However, the process of switching from Supervisor Mode (non-secure) to Secure Monitor Mode is not straightforward and requires careful consideration of the processor’s security state and configuration.

In the ARMv7-A architecture, the processor operates in either the secure state or the non-secure state. The Secure Configuration Register (SCR) in the CP15 system control coprocessor controls the security state and related features. The SCR is accessible only in secure privileged modes, such as Secure Monitor Mode. Attempting to access the SCR from a non-secure state results in an undefined instruction exception, as observed in the error logs.

The key challenge lies in the fact that the TI AM3358 Sitara SoC, by default, operates in the non-secure state. This means that the processor boots into a non-secure mode, and the secure world is not directly accessible without proper initialization. The secure state is typically initialized by the boot ROM or a secure bootloader, which sets up the secure environment and transitions the processor to the non-secure state before handing control to the operating system.

Secure Configuration Register Access and Security State Management

The Secure Configuration Register (SCR) is a critical component in managing the security state of the ARM Cortex-A8 processor. The SCR controls various security-related features, including the enablement of the secure state, the handling of secure monitor calls, and the configuration of the non-secure memory map. Access to the SCR is restricted to secure privileged modes, such as Secure Monitor Mode, and attempting to access it from a non-secure state results in an undefined instruction exception.

The SCR can be accessed using the following CP15 instructions:

MRC p15, 0, <Rd>, c1, c1, 0 ; Read Secure Configuration Register
MCR p15, 0, <Rd>, c1, c1, 0 ; Write Secure Configuration Register

However, these instructions will only succeed if executed in a secure privileged mode. In the non-secure state, the processor will raise an undefined instruction exception, as observed in the error logs. This behavior is by design, as it prevents unauthorized access to the secure state from the non-secure world.

To transition to the secure state and access the SCR, the processor must first enter Secure Monitor Mode. This is typically done using the Secure Monitor Call (SMC) instruction, which generates a secure monitor exception. The SMC instruction is used to request services from the secure world, such as switching to the secure state or accessing secure resources.

The SMC instruction is executed as follows:

SMC #<imm4> ; Secure Monitor Call with immediate value

The immediate value is used to specify the service being requested. The secure monitor exception handler, which runs in Secure Monitor Mode, interprets the immediate value and performs the requested operation. This handler is part of the secure firmware and is responsible for managing transitions between the secure and non-secure states.

Implementing Secure Monitor Mode Transition and SCR Access

To successfully transition to Secure Monitor Mode and access the Secure Configuration Register, the following steps must be taken:

1. Secure Firmware Initialization: The secure firmware, typically part of the boot ROM or a secure bootloader, must initialize the secure environment. This includes setting up the secure memory map, configuring the SCR, and installing the secure monitor exception handler. The secure firmware must also ensure that the processor transitions to the non-secure state before handing control to the operating system.

2. Secure Monitor Exception Handler: The secure monitor exception handler is responsible for handling SMC instructions and managing transitions between the secure and non-secure states. The handler must be installed in the secure world and configured to handle the specific SMC immediate values used by the system.

3. SMC Instruction Execution: To transition to the secure state, the operating system or a privileged application must execute the SMC instruction with the appropriate immediate value. This generates a secure monitor exception, which transfers control to the secure monitor exception handler.

4. Secure State Transition: The secure monitor exception handler interprets the SMC immediate value and performs the requested operation. This may include switching to the secure state, accessing the SCR, or performing other secure operations. Once the operation is complete, the handler must return control to the non-secure state.

5. SCR Access: Once in the secure state, the SCR can be accessed using the CP15 instructions mentioned earlier. The SCR can be read or modified as needed, and the secure state can be exited by returning control to the non-secure state.

The following code snippet demonstrates the basic structure of a secure monitor exception handler:

void secure_monitor_handler(uint32_t smc_imm) {
    switch (smc_imm) {
        case SMC_ENTER_SECURE:
            // Transition to secure state
            enter_secure_state();
            break;
        case SMC_EXIT_SECURE:
            // Transition to non-secure state
            exit_secure_state();
            break;
        case SMC_READ_SCR:
            // Read Secure Configuration Register
            uint32_t scr_value = read_scr();
            return_scr_value(scr_value);
            break;
        case SMC_WRITE_SCR:
            // Write Secure Configuration Register
            write_scr(get_scr_value());
            break;
        default:
            // Handle unknown SMC immediate value
            handle_unknown_smc(smc_imm);
            break;
    }
}

In this example, the secure monitor exception handler handles four SMC immediate values: SMC_ENTER_SECURE, SMC_EXIT_SECURE, SMC_READ_SCR, and SMC_WRITE_SCR. The handler performs the appropriate operation based on the immediate value and returns control to the non-secure state once the operation is complete.

Secure State Transition and SCR Access Example

The following example demonstrates how to transition to the secure state, access the SCR, and return to the non-secure state:

void enter_secure_state() {
    // Save non-secure state
    save_non_secure_state();

    // Transition to secure state
    asm volatile("smc #0");

    // Restore non-secure state
    restore_non_secure_state();
}

uint32_t read_scr() {
    uint32_t scr_value;
    asm volatile("mrc p15, 0, %0, c1, c1, 0" : "=r"(scr_value));
    return scr_value;
}

void write_scr(uint32_t scr_value) {
    asm volatile("mcr p15, 0, %0, c1, c1, 0" : : "r"(scr_value));
}

void exit_secure_state() {
    // Save secure state
    save_secure_state();

    // Transition to non-secure state
    asm volatile("smc #1");

    // Restore secure state
    restore_secure_state();
}

In this example, the enter_secure_state function transitions to the secure state by executing the SMC instruction with an immediate value of 0. The read_scr and write_scr functions access the SCR using the CP15 instructions. The exit_secure_state function transitions back to the non-secure state by executing the SMC instruction with an immediate value of 1.

Conclusion

Transitioning to Secure Monitor Mode and accessing the Secure Configuration Register in the ARM Cortex-A8 processor requires careful management of the processor’s security state. The secure firmware must initialize the secure environment and install the secure monitor exception handler. The operating system or a privileged application can then use the SMC instruction to transition to the secure state and access the SCR. By following the steps outlined in this guide, developers can successfully manage the security state of the ARM Cortex-A8 processor and access the Secure Configuration Register.