Author: System on Chips

SVC Pendability and Exception Entry Behavior in ARM Cortex-M The SuperVisor Call (SVC) exception in ARM Cortex-M processors is a critical mechanism for implementing system calls and transitioning between privilege levels. However, its behavior during exception entry and handling can be nuanced, particularly when higher-priority interrupts preempt the SVC exception. The ARMv7-M architecture defines specific…

ARM Trusted Firmware Boot Process and Cortex-A57 Workarounds The issue revolves around the failure to boot ARM Trusted Firmware (ATF) on a QEMU virtual machine emulating a Cortex-A57 processor. The user is attempting to run bare-metal firmware at Exception Level 2 (EL2) using ATF to manage multi-core bootstrapping via the Power State Coordination Interface (PSCI)….

Cortex-M7 VFMA Instruction Pipeline Behavior and Performance Degradation The Cortex-M7’s VFMA (Vector Fused Multiply-Add) instruction is a powerful floating-point operation that combines multiplication and addition in a single cycle, theoretically improving performance for computationally intensive tasks such as polynomial evaluation. However, the observed behavior in the provided benchmarks reveals significant pipeline stalls and performance degradation…

SMC Call Misrouting to Sync Exception at NS.EL1 Instead of EL3 When working with ARM Cortex-A53 processors, particularly in systems requiring secure and non-secure world transitions, a common issue arises when Secure Monitor Calls (SMC) fail to trap to Exception Level 3 (EL3) as expected. Instead, the processor remains in Non-Secure EL1 and triggers a…

NVIC Set Enable and Clear Enable Register Behavior in Cortex-M4 The behavior of the Nested Vectored Interrupt Controller (NVIC) in ARM Cortex-M4 processors, particularly regarding the Set Enable (ISER) and Clear Enable (ICER) registers, can be a source of confusion for developers. When enabling an interrupt using the NVIC_ISER register, it is observed that the…

Cache and MMU Enable/Disable Sequence in Bootloader Initialization When developing a custom bootloader for an ARM Cortex-A9 processor, such as the one found in the NXP i.MX6 DualLite, managing the caches and Memory Management Unit (MMU) is critical to ensure proper system initialization. The bootloader must initialize a large block of memory (e.g., 50 MB)…

Cortex-A7 L1 Data and Unified Cache Disablement in AMP Mode The ARM Cortex-A7 processor, widely used in embedded systems for its balance of performance and power efficiency, exhibits a unique behavior when operating in Asymmetric Multiprocessing (AMP) mode. Specifically, when the SMP (Symmetric Multiprocessing) bit in the ACTLR (Auxiliary Control Register) is cleared to enable…

ARM Cortex-R Vector Table Transition from High to Low Address When working with ARM Cortex-R series processors, transitioning between vector tables located at different memory addresses (e.g., from high vectors at 0xFFFF0000 to low vectors at 0x00000000) is a critical operation that requires careful handling of system registers and memory barriers. The process involves modifying…

ARM Cortex-M7 Semihosting File I/O Failures in DS-5 Semihosting is a mechanism that allows ARM-based embedded systems to communicate with a host computer for debugging and development purposes. It enables the target device to use the host’s resources, such as file I/O, console input/output, and other system services. However, when implementing semihosting on an ARM…

Cortex-M0 ROM-to-RAM Program Counter Transition Challenges The Cortex-M0 microcontroller unit (MCU) is a widely used ARM processor core known for its simplicity and efficiency in embedded systems. One common design scenario involves executing firmware from Read-Only Memory (ROM) upon power-up, followed by a transition to executing firmware from Random-Access Memory (RAM). This transition is typically…