Author: System on Chips

ARM Cortex-A78 DC ZVA Instruction Alignment Fault During Linux Kernel Boot DC ZVA Instruction Execution Failure in __pi_memset Function The ARM Cortex-A78 processor is encountering an alignment fault when executing the DC ZVA (Data Cache Zero by VA) instruction within the __pi_memset function during the Linux kernel boot process. The __pi_memset function is part of…

Cortex-R8 SMP Core 0 Stuck in WFE State After SEV Execution In a multi-core Cortex-R8 system, Core 0 enters a Wait For Event (WFE) state while waiting for a spinlock. Despite another core executing a Send Event (SEV) instruction, Core 0 fails to wake up and resume execution. This behavior indicates a breakdown in the…

ARM Cortex-M33 IBUSERR Flag Generation and HardFault/BusFault Scenarios The IBUSERR flag, represented by bit 0 in the BusFault Status Register (BFSR), is a critical indicator of instruction bus errors on ARM Cortex-M33 processors. When the IBUSERR flag is set, it signifies that the processor has encountered a fault during an instruction fetch operation. This fault…

GIC-600 ACE-Lite Slave Port and Its Role in Register Access The Generic Interrupt Controller 600 (GIC-600) is a critical component in ARM-based systems, responsible for managing interrupts across multiple processors and peripherals. One of the key architectural features of the GIC-600 is its ACE-Lite slave port, which is used for accessing its internal registers. The…

ARM Cortex-A9 Vector Table Remapping and IRQ Handling Misalignment The ARM Cortex-A9 processor, like other ARMv7-A architecture processors, relies on a vector table to handle exceptions and interrupts. The vector table contains addresses of exception handlers, and its base address is stored in the Vector Base Address Register (VBAR). Properly remapping the vector table is…

NEON Instruction Execution Failure in NSEL1 with HCR_EL2.ID and HCR_EL2.CD Set to 1 The core issue revolves around the failure of NEON instructions to execute in Non-Secure EL1 (NSEL1) when the HCR_EL2 register’s ID (Instruction Cache Disable) and CD (Data Cache Disable) bits are both set to 1. Specifically, the NEON instruction str q0, [x1,…

Cortex-A9 MPCore IRQ Vector Misdirection During Local Timer Interrupt The Cortex-A9 MPCore processor, when configured to handle interrupts via the Generic Interrupt Controller (GIC), is experiencing a misdirection of the interrupt vector. Specifically, when a local timer interrupt (vector 29) is triggered, the processor incorrectly jumps to the Supervisor Call (SVC) exception handler instead of…

Identifying ARM CPU Cores on Die: Feasibility and Techniques Reverse engineering an ARM CPU core on a die is a complex but feasible task for skilled engineers with access to advanced tools and techniques. The process involves decapsulating the integrated circuit (IC), imaging the die using high-resolution microscopy, and analyzing the physical layout to identify…

ARMv8-M Secure Stack Pointer Vulnerability Overview (CVE-2020-16273) The ARMv8-M architecture introduces a security extension known as TrustZone for ARM Cortex-M processors, which partitions the system into Secure and Non-secure worlds. This partitioning is designed to isolate sensitive code and data in the Secure world from potentially malicious or untrusted code in the Non-secure world. A…

ARM Cortex-A78 Atomic Instruction Execution Failure During Kernel Boot The issue at hand involves the ARM Cortex-A78 CPU failing to execute atomic instructions, specifically Load-Exclusive (LDXR) and Store-Exclusive (STXR), during the Linux kernel boot process. The kernel version in use is 5.10.39, and the bootloader is U-Boot 2021.10-rc2. The problem manifests when the kernel attempts…