Author: System on Chips

Understanding AXI Write Response Requirements and Signal Behavior The ARM AMBA AXI protocol defines a robust mechanism for write transactions, including the generation and handling of write responses. A write transaction in AXI involves the transfer of data from a manager (master) to a subordinate (slave) and requires the subordinate to acknowledge the completion of…

ARMv8.9 PIE/POE Feature Enabling Leads to Linux Boot Stalling The ARMv8.9 architecture introduces Permission Indirection Extensions (PIE) and Permission Overlay Extensions (POE), which are advanced memory protection mechanisms designed to enhance security and flexibility in memory management. These features allow for more granular control over memory permissions by introducing indirection layers and overlays in the…

Locked AXI Read-Write Transaction Ordering and Multi-Slave Locking The core issue revolves around the behavior of locked AXI transactions, particularly when dealing with back-to-back read and write operations, as well as the implications of locking multiple slaves simultaneously. Locked transactions in AXI are designed to ensure atomicity, meaning that once a master initiates a locked…

ARM Cortex-A53 APU Cluster ID Bit Allocation and Interconnect Routing The Zynq UltraScale+ platform integrates an ARM Cortex-A53 APU cluster with a NIC-400 interconnect, which is responsible for managing transactions between the Processing System (PS) and the Programmable Logic (PL). The ID width of the ports connecting the PS to the PL is 16 bits,…

AXI Master Reset Leading to NIC-400 Bus Matrix Deadlock In ARM-based SoC designs utilizing the AXI protocol and the NIC-400 interconnect, improper reset sequencing of an AXI master can lead to a bus matrix deadlock. This deadlock occurs when outstanding AXI transactions are not completed before the master is reset, causing the NIC-400 interconnect to…

ARM Cortex-M3 DesignStart Failing in Vivado Versions Beyond 2022.1 The ARM Cortex-M3 DesignStart program provides a cost-effective and accessible way for developers to integrate ARM Cortex-M3 cores into their FPGA designs. However, a significant issue has emerged where the Cortex-M3 DesignStart IP fails to function correctly in Xilinx Vivado versions newer than 2022.1. This incompatibility…

ARM Cortex-A53 Tarmac Trace Generation in Gate-Level Simulation The generation of Tarmac traces during gate-level simulation for ARM Cortex-A53 processors is a complex but critical task for debugging and performance analysis. Tarmac traces provide a detailed log of the processor’s execution, including instruction flow, register updates, and memory accesses. While Tarmac traces are typically generated…

ARM Cortex-A53 L2MERRSR_EL1 Error Parsing and Cache Organization The ARM Cortex-A53 processor incorporates a shared L2 cache, which is a critical component for system performance and reliability. The L2 Memory Error Reporting Status Register (L2MERRSR_EL1) is a key register used for diagnosing faults in the L2 cache. In the context of the Zynq UltraScale+ (ZU+)…

Synchronous Exception SPx During MMU Enable in BL1 Stage The issue described involves a failure during the reboot process on an ARM Fixed Virtual Platform (FVP) RDV2 platform. Specifically, the failure occurs in the BL1 stage when attempting to enable the Memory Management Unit (MMU) in EL3 mode. The failure manifests as a Synchronous Exception…

PSTATE Capture During Denied Power State Transitions In the AMBA Low Power Interface (LPI) specification, the capture of PSTATE (Power State) during specific conditions involving PREQ (Power Request) and PDENY (Power Deny) signals is a critical aspect of power management. The specification outlines that PSTATE can be captured when a request is denied, specifically when…