Author: System on Chips

ARM Cortex-R52 IMP_CBAR Access in AArch32 Mode Fails with Undefined Instruction The ARM Cortex-R52 processor, when operating in AArch32 mode, provides access to the Implementation-Defined Configuration Base Address Register (IMP_CBAR). This register holds the physical base address of the memory-mapped Generic Interrupt Controller (GIC) Distributor registers. However, during simulation using the ARMv8-R AEM Fixed Virtual…

Non-Contiguous Memory Allocation in ARM FVP Host Address Space When attempting to remap Linux Host PCI memory into an ARM Fixed Virtual Platform (FVP) running Linux in the non-secure world, a significant challenge arises due to the non-contiguous allocation of pages in the FVP’s host address space. The FVP allocates pages that are adjacent but…

SMMUv3TestEngine Integration Challenges in ARM FVP_Base_RevC-2xAEMvA The integration of the SMMUv3TestEngine into the ARM FVP_Base_RevC-2xAEMvA platform presents a unique set of challenges, particularly when attempting to verify a DMA-capable device that is not on the PCIe bus. The SMMUv3TestEngine, while a powerful tool for simulating System Memory Management Unit (SMMU) behavior, lacks comprehensive documentation, making…

AHB Interconnect Early Burst Termination Behavior During Multi-Master Operations In an ARM-based SoC design utilizing the AHB (Advanced High-performance Bus) protocol, early burst termination can introduce significant challenges, particularly when multiple masters are accessing different slaves concurrently. The scenario described involves two masters, M0 and M1, and two slaves, S0 and S1. Master M0 initiates…

ARM UMC55ULP Sign-Off Guidelines and FFG/SSG Corner Availability The ARM UMC55ULP sign-off guidelines explicitly recommend using only the Fast-Fast (FF) and Slow-Slow (SS) corners for design sign-off. However, the official Process Design Kit (PDK) provided by the foundry includes additional corners such as Fast-Fast Global (FFG) and Slow-Slow Global (SSG). This discrepancy raises questions about…

AHB Interconnect Master Handover with Split HREADY Signaling In Advanced High-performance Bus (AHB) interconnects, the handover between masters during data transfers is a critical operation that ensures seamless communication between multiple masters and slaves. A common challenge arises when a master is stalled during the data phase due to a low HREADY signal from the…

Persistent HREADYOUT Signal in AHB Slave Modules In ARM Cortex-M based System-on-Chip (SoC) designs utilizing the Advanced High-performance Bus (AHB) protocol, a common observation is that the HREADYOUT signal from slave modules is often hardwired to a constant value of 1. This behavior can be perplexing, especially when attempting to monitor data transactions such as…

AHB-Lite Protocol Constraints on Wait State Handling The AHB-Lite protocol, a simplified version of the Advanced High-performance Bus (AHB), is designed for single-master systems and is widely used in ARM-based SoCs. One of the critical aspects of the AHB-Lite protocol is its handling of wait states, which are signaled by the HREADY signal. When HREADY…

NIC-400 Timing Closure Challenges in Multi-Interface Configurations The NIC-400 interconnect is a highly configurable and scalable network interconnect from ARM, widely used in ARM-based SoCs to manage communication between multiple masters and slaves. One of the critical aspects of NIC-400 configuration is ensuring timing closure, which involves adding register slices to interfaces to meet timing…

Cortex-R82 Dcache Enable Failure in SMP Mode During Boot Process The Cortex-R82 is a high-performance, real-time processor designed for applications requiring deterministic behavior and high throughput. One of its key features is the ability to operate in Symmetric Multiprocessing (SMP) mode, where multiple cores execute tasks concurrently. However, enabling the Data Cache (Dcache) in SMP…