ARM Cortex-A9 and PL310 Cache Coherency Issue with Non-Cacheable Writes and Shared Override Bit
ARM Cortex-A9 and PL310 Cache Behavior During Non-Cacheable Writes The ARM Cortex-A9 processor, when paired with the PL310 L2 cache controller, exhibits complex behavior during non-cacheable writes, especially when the shared override bit is set. The core issue revolves around whether a non-cacheable write operation from an external master (such as a DMA controller) will…