Author: System on Chips

ARM Cortex-M55 Debugger Reconnection Issue After Warm Reset The Cortex-M55 is a highly capable processor designed for embedded systems, particularly in applications requiring machine learning and digital signal processing. However, during development and debugging, a critical issue arises where the debugger cannot reconnect to the Cortex-M55 after a warm reset (sysresetreq) without performing a hard…

PMU Event Logging Overhead Impact on Cortex-R4 CPU Idle Time The Cortex-R4 processor, a member of ARM’s real-time processor family, is widely used in applications requiring high reliability and deterministic performance, such as automotive systems, storage controllers, and modems. One of its key features is the Performance Monitoring Unit (PMU), which allows developers to profile…

ARM Cortex-A53 Cache Coherency Breakdown During Warm Start The issue described revolves around the ARM Cortex-A53 cores experiencing cache coherency problems during a warm start sequence, specifically when transitioning between 64-bit and 32-bit execution modes. In a cold start scenario, all four A53 cores execute bare metal code in 64-bit mode before jumping to a…

ARM DSU Cluster Architecture and Linux Scheduling Constraints The scenario involves an ARM-based System-on-Chip (SoC) with two Dynamic Shared Unit (DSU) clusters: Cluster0, which consists of 4 Cortex-A76 cores and 4 Cortex-A55 cores, and Cluster2, which has 4 Cortex-A55 cores. Each cluster has its own L3 cache and connects to a Network-on-Chip (NoC). The SoC…

ARM Cortex-R5F MPU and Cache Interaction Leading to Stack Corruption The ARM Cortex-R5F processor integrates a Memory Protection Unit (MPU) and cache subsystems that are critical for ensuring memory safety and performance in real-time embedded systems. However, enabling the MPU can lead to unexpected behavior, such as stack corruption, particularly when caches are enabled. This…

ARM Cortex-M4 Cache Coherency Problems During DMA Transfers The Neoverse N1 microarchitecture, a high-performance ARM core designed for server and infrastructure workloads, exhibits unexpected pipeline behavior when executing specific arithmetic instructions with large shift values. Specifically, the adds instruction with a logical shift left (LSL) greater than 4, such as adds x3, x4, x5, lsl…

Cortex-M7 ALU Overflow Detection Challenges The ARM Cortex-M7 processor, known for its high performance and efficiency, is widely used in embedded systems requiring real-time processing capabilities. One of the critical aspects of ensuring reliable operation in such systems is the detection and handling of arithmetic logic unit (ALU) overflow. Overflow occurs when the result of…

Cortex-R5 MicroSCU Role in Multi-Core Coherency The Cortex-R5 processor, a member of ARM’s real-time processor family, is widely used in embedded systems requiring deterministic performance and high reliability. One of the key architectural features of the Cortex-R5 is its optional MicroSCU (Micro Snoop Control Unit), which plays a critical role in maintaining cache coherency in…

ARM Assembly Coding Formats: Legacy AREA vs. GNU .global Directives When working with ARM assembly, developers often encounter two distinct coding formats: the legacy AREA directive used in the ARM proprietary assembler (armasm) and the .global directive commonly found in GNU assembler (as) or ARM’s armclang integrated assembler. These formats are not interchangeable and are…

ARM Cortex-M23 TrustZone Branch Instruction Behavior in Non-Secure State The ARM Cortex-M23 processor, which implements the ARMv8-M architecture, introduces TrustZone security extensions to enable secure and non-secure state separation. A critical aspect of this architecture is the handling of branch instructions, particularly when transitioning between secure and non-secure states. One specific issue arises when executing…