Author: System on Chips

Cortex-R52 Startup File Requirements and Challenges The Cortex-R52 is a high-performance, real-time processor designed for safety-critical applications, often used in automotive, industrial, and aerospace systems. Writing a startup file for the Cortex-R52 involves initializing the processor, setting up the memory map, configuring the stack pointers, and preparing the environment for the main application. Unlike the…

Cortex-R82 MP Generation Failure in Socrates v1.7.0 The issue at hand revolves around the inability to generate a Cortex-R82 MP (Multi-Processor) configuration using the Socrates IP configuration tool version 1.7.0. Despite having the necessary IP bundle (MP130-BU-50000-r1p0-00lac0), the Cortex-R82 MP does not appear in the IP catalog list within Socrates. This prevents the user from…

Understanding the Difference Between Global System Counter and Cycle Counts The ARM Cortex-A53 processor, like many modern ARM cores, provides multiple mechanisms for tracking time and performance metrics. Two of the most commonly used mechanisms are the Global System Counter and the Performance Monitors Cycle Count Register (PMCCNTR_EL0). These two counters serve different purposes and…

ARM Cortex-M33 ACI Implementation Challenges for 2D Convolution Optimization The Cortex-M33 processor, part of Arm’s Cortex-M series, is a powerful embedded processor designed for applications requiring a balance of performance, power efficiency, and security. One of its standout features is the support for Arm Custom Instructions (ACI), which allows silicon vendors to extend the processor’s…

ARM Cortex-M4 Power Consumption During DSP Operations When working with ARM Cortex-M4 microcontrollers, power consumption is a critical consideration, especially in battery-powered or energy-constrained applications. The Cortex-M4, with its DSP extensions and floating-point unit (FPU), is often used for digital signal processing (DSP) tasks such as Fast Fourier Transform (FFT) calculations. Two popular libraries for…

Cortex-M4F FPU Hard Fault During Float Literal Multiplication The Cortex-M4F processor, equipped with a Floating Point Unit (FPU), is designed to accelerate floating-point computations, making it ideal for applications requiring high-performance mathematical operations. However, a common issue arises when attempting to multiply a float variable by a float literal, resulting in a system crash. This…

ARM Cortex-M Timers and the Prevalence of Down-Counters In ARM Cortex-M microcontrollers, timers are a critical component for real-time operations, task scheduling, and peripheral control. A notable design choice in these systems is the use of down-counters rather than up-counters. This preference is rooted in both software efficiency and hardware optimization. Down-counters, which decrement from…

ARM Cortex-A53 Exception Handling and Mode Switching Fundamentals The ARM Cortex-A53 processor, part of the ARMv8-A architecture, supports multiple exception levels (ELs) and execution states (aarch32 and aarch64). Exception levels provide a hierarchical privilege model, with EL3 being the highest privilege level typically used for secure monitor code, EL2 for hypervisor functionality, and EL1 for…

Core 1 Fails to Execute from QSPI Flash with Incorrect Program Counter Jump When attempting to run bare-metal code on both cores of an ARM Cortex-A9 dual-core processor within an Intel Cyclone V SoC, Core 0 executes successfully from QSPI flash, while Core 1 fails to start correctly. Instead of jumping to its designated entry…

Core 1 Program Counter Misdirection to 0xFEBAF5E8 The issue at hand involves the failure of Core 1 to execute its designated code when booting from QSPI flash on an Intel Cyclone V SoC with an ARM Cortex-A9 dual-core processor. While Core 0 operates as expected, Core 1’s program counter (PC) incorrectly jumps to the address…