Author: System on Chips

VDDCE and VDDPE Power Sequencing Violation in Power Down Mode The core issue revolves around the improper power pin connection strategy for the Arm Artisan 14nm 14LPP High-Speed Single-Port SRAM, specifically concerning the VDDCE and VDDPE power pins. The design team plans to connect VDDCE and VDDPE to the same power net, which simplifies the…

Understanding the Role of Burst Transfers in AHB Protocol The Advanced High-performance Bus (AHB) protocol, part of the ARM AMBA (Advanced Microcontroller Bus Architecture) family, is widely used in System-on-Chip (SoC) designs for high-performance data transfers between masters and slaves. One of the key features of AHB is its support for burst transfers, which allows…

APB Protocol Constraints and Multiple Transfer Scenarios The Advanced Peripheral Bus (APB) is a part of the ARM AMBA protocol family, designed for low-power, low-complexity peripheral interfacing. Unlike AXI or AHB, APB does not support burst transfers. Each transfer on the APB bus is treated as an independent operation, and only one transfer can be…

AHB-Lite Protocol State Machine Implementation Challenges The AHB-Lite protocol, a simplified version of the Advanced High-performance Bus (AHB) protocol, is widely used in ARM-based System-on-Chip (SoC) designs for its efficiency in handling data transfers between masters and slaves. One of the critical aspects of implementing the AHB-Lite protocol is the design of state machines that…

AHB WRAP Transactions and Unaligned Address Handling The Advanced High-performance Bus (AHB) protocol, part of the ARM AMBA specification, is widely used in SoC designs for its high-performance and efficient data transfer capabilities. One of the key features of AHB is its support for burst transactions, including WRAP bursts, which are particularly useful for cache…

Multiplexing a Single Databus into Separate Read/Write Buses Using Inout Ports In ARM-based SoC designs, efficient data transfer mechanisms are critical for performance and resource optimization. A common scenario involves multiplexing a single bidirectional databus into separate read and write buses to streamline data flow. This is often achieved using inout ports in the hardware…

AHB-Lite Protocol’s Pipelined Transfer Requirements The AHB-Lite protocol, a subset of the Advanced Microcontroller Bus Architecture (AMBA) family, is designed to facilitate high-performance communication between masters and slaves in a system-on-chip (SoC). One of the key features of the AHB-Lite protocol is its pipelined transfer mechanism, which separates the address phase and data phase of…

APB Write Transaction Behavior with PSTRB = "0000" The Advanced Peripheral Bus (APB) protocol, part of the ARM AMBA (Advanced Microcontroller Bus Architecture) family, is designed for low-power, low-complexity peripheral interfacing. One of the key signals in APB write transactions is the PSTRB (Peripheral Strobe) signal, which indicates the validity of each byte lane during…

Processor Load/Store Architecture Constraints with AHB Interface Requirements The integration of an AHB (Advanced High-performance Bus) interface into a processor with a load/store architecture presents a significant challenge, particularly when the processor is designed with a single bidirectional data bus for both input and output operations. The AHB protocol, as defined by ARM, mandates separate…

ASB-to-APB Communication Challenges in Multi-Clock Domain Systems The communication between the Advanced System Bus (ASB) and the Advanced Peripheral Bus (APB) in an AMBA-based System-on-Chip (SoC) presents a unique set of challenges due to the inherent differences in their operating frequencies and protocols. ASB, being a high-performance bus, typically operates at a higher frequency to…