Author: System on Chips

SYST_CVR Register Access Violation in User Mode on ARM Cortex-M33 The ARM Cortex-M33 processor, part of the ARMv8-M architecture, is designed with a robust security model that includes privilege levels to separate user code from system-level operations. One of the key features of this architecture is the ability to restrict access to certain registers and…

ARM Cortex-M55 PMU Cycle Counter Returning Zero During Code Execution The Performance Monitoring Unit (PMU) in the ARM Cortex-M55 processor is a critical tool for measuring CPU cycles during code execution. However, a common issue arises when the PMU cycle counter returns zero, even though the code compiles and runs without errors. This problem can…

Cortex-R52+ Floating-Point Register Corruption in ISRs The Cortex-R52+ processor, based on the Armv8-R AArch32 architecture, exhibits unexpected behavior when floating-point calculations are performed within interrupt service routines (ISRs). Specifically, floating-point register values may become corrupted or inconsistent across multiple ISR invocations. This issue arises due to the architecture’s design, which does not automatically save and…

MEMATTR Signals in Cortex-M4: AHB-Lite Protocol Discrepancy The ARM Cortex-M4 processor utilizes the AMBA AHB-Lite 3 bus architecture, which is a simplified version of the Advanced High-performance Bus (AHB) protocol. AHB-Lite is designed to reduce complexity by removing features such as bus arbitration, burst support, and split transactions, making it suitable for single-master systems like…

ARM Cortex-M33 Linker Errors During Compilation of liblc3 Library When compiling Google’s liblc3 library for the Cortex-M33 target using the arm-none-eabi-gcc toolchain, linker errors frequently arise. These errors are particularly perplexing because the same library compiles successfully for Cortex-M3 and Cortex-M4 targets, which are based on the Armv7-M architecture. The Cortex-M33, however, is based on…

Understanding AXI4 Unaligned WRITE Transfers and WSTRB Signaling In the AXI4 protocol, unaligned WRITE transfers occur when the starting address (AWADDR) is not aligned to the data width specified by AWSIZE. For example, if AWSIZE is set to 2 (indicating a 32-bit transfer), the starting address should ideally be aligned to a 4-byte boundary (e.g.,…

ARM SBSA Watchdog Timer Pretimeout Feature Overview The ARM Server Base System Architecture (SBSA) watchdog timer (WDT) is a critical component in ensuring system reliability by providing a mechanism to recover from system hangs or software failures. The SBSA watchdog timer operates in two modes: single-stage and double-stage. In single-stage mode, the watchdog timer triggers…

APB5 Parity Bit Generation and Timing Constraints The Advanced Peripheral Bus (APB) is a part of the ARM Advanced Microcontroller Bus Architecture (AMBA) and is widely used in low-bandwidth, low-power peripheral interfaces. APB5, the latest version of the APB protocol, introduces several enhancements, including parity checking for error detection. Parity checking is a simple yet…

ARM Cortex-M4 Memory Access Ordering: Architectural Guarantees vs. Implementation-Specific Behavior The ARM Cortex-M4 processor, like other ARM Cortex-M series processors, is designed with a focus on deterministic real-time performance and low-latency interrupt handling. A critical aspect of its design is memory access ordering, which governs how the processor handles reads and writes to memory. The…

ARM Cortex-A55 DSU Write Issuing Capability and Outstanding Transactions Analysis The ARM Cortex-A55 is a highly efficient mid-range CPU core designed for power-efficient performance in mobile and embedded applications. It is often paired with the DynamIQ Shared Unit (DSU) to manage shared resources among multiple cores in a cluster. One critical aspect of the Cortex-A55…