Author: System on Chips

ARM Cortex-A76 Cache Behavior During Matrix Column Reads with Prefetching The observed performance degradation despite an improved L2 cache hit rate on the ARM Cortex-A76 processor, as seen in the matrix column read program, is a complex issue that involves multiple layers of cache hierarchy and prefetching mechanisms. The Cortex-A76, used in the Raspberry Pi…

Activation Control, Data Capture, and Secure Operation Requirements When designing an ASIC with functionalities such as activation control, data capture, data aggregation, operational feedback, data retrieval, and secure operation, the choice of microcontroller unit (MCU) is critical. The ARM Cortex-M3, Cortex-M4, and Cortex-M33 are all viable candidates, but each has distinct architectural features that make…

ARM Cortex-ETM Trace Configuration and ATVALID Signal Failure The ARM Embedded Trace Macrocell (ETM) is a critical component for real-time instruction tracing in ARM-based systems, enabling developers to capture and analyze the execution flow of their software. The ATVALID signal, which indicates that the trace unit is ready to output valid trace data, is a…

SYST_CVR Register Access Violation in User Mode on ARM Cortex-M33 The ARM Cortex-M33 processor, part of the ARMv8-M architecture, is designed with a robust security model that includes privilege levels to separate user code from system-level operations. One of the key features of this architecture is the ability to restrict access to certain registers and…

Enabling CCR.DIV_0_TRP and Resulting Exceptions The Configuration Control Register (CCR) in ARM Cortex-M processors is a critical register that controls various system behaviors, including the handling of specific faults such as divide-by-zero errors. The CCR.DIV_0_TRP bit, when enabled, configures the processor to trap divide-by-zero operations, allowing developers to handle such errors programmatically rather than allowing…

Cortex-R52+ Floating-Point Register Corruption in ISRs The Cortex-R52+ processor, based on the Armv8-R AArch32 architecture, exhibits unexpected behavior when floating-point calculations are performed within interrupt service routines (ISRs). Specifically, floating-point register values may become corrupted or inconsistent across multiple ISR invocations. This issue arises due to the architecture’s design, which does not automatically save and…

ARM Cortex-M55 PMU Cycle Counter Returning Zero During Code Execution The Performance Monitoring Unit (PMU) in the ARM Cortex-M55 processor is a critical tool for measuring CPU cycles during code execution. However, a common issue arises when the PMU cycle counter returns zero, even though the code compiles and runs without errors. This problem can…

ARM Cortex-M33 Linker Errors During Compilation of liblc3 Library When compiling Google’s liblc3 library for the Cortex-M33 target using the arm-none-eabi-gcc toolchain, linker errors frequently arise. These errors are particularly perplexing because the same library compiles successfully for Cortex-M3 and Cortex-M4 targets, which are based on the Armv7-M architecture. The Cortex-M33, however, is based on…

MEMATTR Signals in Cortex-M4: AHB-Lite Protocol Discrepancy The ARM Cortex-M4 processor utilizes the AMBA AHB-Lite 3 bus architecture, which is a simplified version of the Advanced High-performance Bus (AHB) protocol. AHB-Lite is designed to reduce complexity by removing features such as bus arbitration, burst support, and split transactions, making it suitable for single-master systems like…

ARM SBSA Watchdog Timer Pretimeout Feature Overview The ARM Server Base System Architecture (SBSA) watchdog timer (WDT) is a critical component in ensuring system reliability by providing a mechanism to recover from system hangs or software failures. The SBSA watchdog timer operates in two modes: single-stage and double-stage. In single-stage mode, the watchdog timer triggers…