Author: System on Chips

ARM Cortex-A53 String Library Function Exceptions Due to Misaligned Memory Access The ARM Cortex-A53 processor, a member of the ARMv8-A architecture family, is widely used in embedded systems for its balance of performance and power efficiency. However, developers often encounter issues when running standard library functions such as memset and memcpy on the Cortex-A53 core,…

ARMv8-M TrustZone Register Clearing Behavior: Secure to Non-Secure Transitions The ARMv8-M architecture introduces TrustZone technology, which provides hardware-enforced isolation between secure and non-secure states. This isolation is critical for protecting sensitive data and code in embedded systems. However, the behavior of register clearing during state transitions, particularly from secure to non-secure states, has raised questions…

Cortex-A57 L2 Subsystem Reset Challenges in Multi-Cluster Systems The Cortex-A57 processor, part of ARM’s Cortex-A series, is widely used in high-performance embedded systems, particularly in multi-core and multi-cluster configurations. One of the critical components of the Cortex-A57 architecture is the L2 cache subsystem, which plays a vital role in ensuring efficient data access and system…

ARM Thumb-2 Instruction Set and Register Access Constraints The ARM Thumb-2 instruction set is a hybrid 16/32-bit instruction set that combines the code density advantages of the original Thumb instruction set with the performance benefits of the ARM instruction set. One of the key characteristics of the Thumb-2 instruction set is its ability to access…

GIC500 Interrupt Handling and Cortex-A53 CPU Interface Priority Mismatch The core issue revolves around the handling of interrupts in a system utilizing the ARM Cortex-A53 processor and the GIC500 (Generic Interrupt Controller). Specifically, the problem arises when attempting to bypass the standard End of Interrupt (EOI) mechanism by directly manipulating the GIC500 registers via its…

Cortex-A9 SCU Control Register Enable Bit Behavior Inconsistency The Cortex-A9 MPCore Technical Reference Manual (TRM) has undergone revisions, and a critical discrepancy has been identified in the description of the Snoop Control Unit (SCU) Control Register’s enable bit (Bit 0). In Version g of the manual, Bit 0 is described as enabling the SCU when…

ARM Cortex-M7 DSP Moving Average Implementation Challenges The ARM Cortex-M7 processor, with its advanced DSP capabilities, is often employed in applications requiring high-performance signal processing. One common operation in such applications is the calculation of a moving average, which is used to smooth data streams and reduce noise. The moving average algorithm typically involves maintaining…

ARM Cortex-A53 GPIO Toggling Delays Under High-Frequency Operation When developing a bit-banging driver for a Raspberry Pi 3 (equipped with a quad-core ARM Cortex-A53 processor), unexpected delays in GPIO toggling at high frequencies (approximately 1 MHz) were observed. These delays manifest as gaps in the signal, sometimes exceeding 5 microseconds, when monitored with an oscilloscope….

ETM Register Access Challenges on Cortex-M4 Without External Debugging Tools The Embedded Trace Macrocell (ETM) is a powerful feature in ARM Cortex-M4 processors, enabling real-time instruction and data tracing for debugging and performance analysis. However, accessing ETM registers and logs without an external debug kit presents significant challenges, particularly when working with development boards like…

ARM Cortex-A53 and Cortex-A9 PMU Architecture and Core-Specific Event Monitoring The Performance Monitoring Unit (PMU) in ARM Cortex-A53 and Cortex-A9 processors is a critical component for profiling and optimizing system performance. The PMU provides hardware counters that allow developers to monitor various microarchitectural events, such as cache hits/misses, branch predictions, and instruction execution counts. Understanding…