Author: System on Chips

QSPI Memory Overflow and SRAM Boot Failures on ARM Musca Board The ARM Musca board, a popular development platform for secure and non-secure world applications, often encounters issues related to memory allocation and boot sequence configuration. One common problem arises when the QSPI (Quad Serial Peripheral Interface) memory overflows due to increased code size, forcing…

ARM Cortex-R52 FreeRTOS Porting Challenges and Compatibility Issues Porting FreeRTOS to the ARM Cortex-R52 processor involves addressing several architectural differences and ensuring compatibility with the specific features of the Cortex-R52. The Cortex-R52 is a high-performance processor designed for real-time applications, featuring a dual-core configuration, advanced memory protection, and support for virtualization. These features necessitate careful…

FreeRTOS Task Scheduling Across Secure and Non-Secure Worlds in ARMv8-M TrustZone The integration of FreeRTOS with ARMv8-M TrustZone on Cortex-M33 processors presents a unique challenge due to the separation of secure and non-secure worlds. The Cortex-M33 processor, part of the ARMv8-M architecture, introduces TrustZone technology, which provides hardware-enforced isolation between secure and non-secure states. This…

ARM Cortex-A53 Executable Text Section Size Discrepancy When compiling a Xilinx hello world application for the ARM Cortex-A53 processor using ARMCC 6.7, the text section size of the resulting executable is significantly larger (~82 KB) compared to the same application compiled with GCC 7.3.1 (~30 KB). This discrepancy is observed despite both compilers using similar…

ARM Cortex-A53 String Library Function Exceptions Due to Misaligned Memory Access The ARM Cortex-A53 processor, a member of the ARMv8-A architecture family, is widely used in embedded systems for its balance of performance and power efficiency. However, developers often encounter issues when running standard library functions such as memset and memcpy on the Cortex-A53 core,…

ARMv8-M TrustZone Register Clearing Behavior: Secure to Non-Secure Transitions The ARMv8-M architecture introduces TrustZone technology, which provides hardware-enforced isolation between secure and non-secure states. This isolation is critical for protecting sensitive data and code in embedded systems. However, the behavior of register clearing during state transitions, particularly from secure to non-secure states, has raised questions…

Cortex-A57 L2 Subsystem Reset Challenges in Multi-Cluster Systems The Cortex-A57 processor, part of ARM’s Cortex-A series, is widely used in high-performance embedded systems, particularly in multi-core and multi-cluster configurations. One of the critical components of the Cortex-A57 architecture is the L2 cache subsystem, which plays a vital role in ensuring efficient data access and system…

GIC500 Interrupt Handling and Cortex-A53 CPU Interface Priority Mismatch The core issue revolves around the handling of interrupts in a system utilizing the ARM Cortex-A53 processor and the GIC500 (Generic Interrupt Controller). Specifically, the problem arises when attempting to bypass the standard End of Interrupt (EOI) mechanism by directly manipulating the GIC500 registers via its…

ARM Thumb-2 Instruction Set and Register Access Constraints The ARM Thumb-2 instruction set is a hybrid 16/32-bit instruction set that combines the code density advantages of the original Thumb instruction set with the performance benefits of the ARM instruction set. One of the key characteristics of the Thumb-2 instruction set is its ability to access…

Cortex-A9 SCU Control Register Enable Bit Behavior Inconsistency The Cortex-A9 MPCore Technical Reference Manual (TRM) has undergone revisions, and a critical discrepancy has been identified in the description of the Snoop Control Unit (SCU) Control Register’s enable bit (Bit 0). In Version g of the manual, Bit 0 is described as enabling the SCU when…