Author: System on Chips

WVALID Assertion Timing and Glitch During AXI Write Data Handshake The issue revolves around the assertion of the WVALID signal in the AXI (Advanced eXtensible Interface) write data channel during a handshake between the master and slave. Specifically, the problem occurs when the master attempts to assert WVALID in the same ACLK cycle where the…

AXI4 Unaligned Transfer Behavior with 32-bit Data on 64-bit Bus In AXI4-based systems, unaligned transfers occur when the starting address of a data transfer does not match the natural alignment boundary of the data width. For example, transferring 32-bit data on a 64-bit bus starting at address 0x001 is an unaligned transfer because the address…

WLAST Assertion Before WVALID and Address Issuance In AXI4-based designs, the timing of the WLAST signal relative to WVALID and the address phase (AW channel) can often lead to confusion, especially when observed in simulation waveforms. The WLAST signal is a critical component of the AXI4 write data channel (W channel), indicating the final transfer…

AXI FIXED Burst WSTRB Calculation and Lane Alignment Issues In AXI4 FIXED burst type transactions, the calculation of the write strobe (WSTRB) and the alignment of byte lanes can be a source of confusion, especially when dealing with unaligned start addresses. The WSTRB signal is critical in AXI transactions as it indicates which byte lanes…

AXI4 Protocol Evolution: The Absence of WID The Advanced eXtensible Interface (AXI) protocol, developed by ARM, has undergone significant evolution from AXI3 to AXI4. One of the most notable changes in AXI4 is the removal of the Write ID (WID) signal, which was present in AXI3. The WID signal in AXI3 was used to support…

ARM Coresight Architecture: ROM Table Integration Complexity The integration of AHB ROM tables into the Coresight system ROM table presents a multifaceted challenge in ARM-based SoC designs. The Coresight architecture, a critical component for debugging and tracing, relies on a hierarchical system of ROM tables to identify and access various debug components. These ROM tables…

CoreSight STM and TPIU Driver Integration Failures in R8A77970 SoC The integration of CoreSight STM (System Trace Macrocell) and TPIU (Trace Port Interface Unit) drivers in the Renesas R8A77970 SoC is encountering significant issues due to missing device tree source (DTS) entries. The absence of critical components such as STM, STM500, ETM4.0, Funnel, Replicator, TMC-ETR,…

ARM-A15 Program Counter and AXI Traffic Debugging Challenges in VCS Simulation When integrating an ARM Cortex-A15 processor into a System-on-Chip (SoC) design, one of the most critical aspects of verification is ensuring visibility into the processor’s execution flow and its interaction with the system via the AXI bus. The Program Counter (PC) is a fundamental…

AXI4 Unaligned Transfer Confusion: Aligned Address vs. Unaligned Address with WSTRB The AXI4 protocol provides flexibility for handling unaligned transfers, but the specification’s phrasing regarding the relationship between the address and write strobes (WSTRB) can lead to confusion. Specifically, the protocol states that a master can either use the low-order address lines to signal an…

ARM DS-5 Linux Project Executable Naming and Extension Inconsistencies When working with ARM DS-5 for Linux project development, one of the common issues that developers encounter is the inconsistency in the naming and extension of the generated executable files. Specifically, some projects generate executables with the .axf extension, while others do not. This inconsistency can…