Author: System on Chips

Tidemark Functionality in AXI Interconnect and Its Impact on AWREADY The Tidemark functionality in the AXI Interconnect PL301 r2p3 is a critical feature that governs the flow control of write transactions between AXI masters and slaves. Tidemark is essentially a threshold mechanism that determines when the interconnect should stall or allow the release of write…

Evolution of AMBA AHB Protocol Generations The AMBA AHB (Advanced High-performance Bus) protocol has undergone significant evolution since its inception, with three major releases that have adapted to the changing requirements of system-on-chip (SoC) designs. Each generation of the AHB protocol has introduced new features, optimizations, and simplifications to address the growing complexity and performance…

AMBA APB Wait States: Impact on Read/Write Transactions and Peripheral Timing The Advanced Peripheral Bus (APB) is a key component of the ARM Advanced Microcontroller Bus Architecture (AMBA) protocol suite, designed for low-power, low-complexity peripheral communication. One of the critical features introduced in AMBA 3 APB is the PREADY signal, which enables the insertion of…

AMBA APB Frequency Limitations and System Complexity The Advanced Microcontroller Bus Architecture (AMBA) Advanced Peripheral Bus (APB) is a low-cost, low-power interface designed for connecting peripherals to a system-on-chip (SoC). Unlike high-performance buses such as AXI or AHB, APB is optimized for simplicity and ease of integration. However, one of the most common questions surrounding…

ARM Cortex-A9 Dual-Core AMP Baremetal Execution Issues The challenge of configuring an Asymmetric Multiprocessing (AMP) baremetal environment on an ARM Cortex-A9 dual-core SoC, such as the one found in the Terasic DE1-SoC, involves running two separate binaries on each core independently. This setup requires careful handling of core initialization, binary loading, and synchronization to ensure…

ARM Base FVP Debugging Challenges with GDB Integration Debugging ARM-based systems using the ARM Base Fixed Virtual Platform (FVP) can be a complex task, especially when integrating third-party tools like GDB. The ARM Base FVP is a cycle-accurate simulation model that emulates ARM-based SoCs, allowing developers to test and debug their software and hardware designs…

SSL Handshake Exception During CMSIS Pack Download The issue at hand involves a failure in the SSL handshake process when attempting to download the CMSIS pack using ARM Development Studio 2020.0. The specific error message is javax.net.ssl.SSLHandshakeException: PKIX path building failed: sun.security.provider.certpath.SunCertPathBuilderException: unable to find valid certification path to requested target. This error indicates that…

AXI ID Width Mismatch in Dual-System ARM Cortex-A15 and Cortex-R7 Integration When integrating two independent ARM-based systems, such as a Cortex-A15 and a Cortex-R7, each operating on separate AXI buses, a common challenge arises when attempting to interconnect these systems for mutual access. The primary issue stems from the AXI ID width configuration, which is…

AMBA AHB SPLIT and RETRY Response Mechanisms The AMBA AHB (Advanced Microcontroller Bus Architecture Advanced High-performance Bus) protocol is a critical component in many ARM-based SoC designs. It facilitates communication between masters (such as CPUs, DMAs, etc.) and slaves (such as memory controllers, peripherals, etc.) over a shared bus. One of the key features of…

ARM FVP Fails to Initialize Graphics Due to libGL Driver Issues The ARM Fixed Virtual Platform (FVP) is a critical tool for simulating ARM-based SoCs, enabling developers to test and validate their designs before hardware availability. However, when running the FVP_MPS2_Cortex-M55 model on an unsupported Linux distribution such as Manjaro, users may encounter libGL errors…