Author: System on Chips

ARM64 SMC Call Concurrency and EL3 Entry Mechanisms The ARM64 architecture introduces a robust mechanism for handling Secure Monitor Calls (SMC), which are essential for transitioning between different exception levels, particularly into EL3, the highest privilege level. SMC calls are synchronous exceptions triggered by software to request services from the Secure Monitor, which operates in…

Illegal Memory Access and Fault Handling Mechanism in Cortex-M3/M4 The ARM Cortex-M3 and Cortex-M4 processors are designed with robust fault handling mechanisms to detect and manage illegal memory accesses, among other issues. When a program attempts to write to an illegal memory location, the processor is expected to trigger a MemManage fault. If the MemManage…

ARMv7 Secure and Non-Secure Mode Stack Pointer Configuration In ARMv7 architectures, the management of stack pointers (SP) in secure and non-secure modes is a critical aspect of system design, particularly when dealing with TrustZone technology. TrustZone introduces a hardware-based security extension that partitions the system into secure and non-secure worlds, each with its own set…

ARM Cortex-M33 NOCP Usage Fault During WIC Sleep and Wake-Up The ARM Cortex-M33 processor, with its TrustZone security extension, introduces a complex interplay between secure and non-secure states, particularly when dealing with the Floating-Point Unit (FPU). A common issue arises when a non-secure thread enters Wait-for-Interrupt (WIC) sleep mode, and a secure handler subsequently wakes…

ARM Cortex-M4 Load/Store Instruction Cycle Variations in Pre/Post-Index Addressing Modes The ARM Cortex-M4 processor, a widely used microcontroller core, employs load and store instructions to move data between memory and registers. These instructions support various addressing modes, including pre-index and post-index addressing. Pre-index addressing calculates the memory address by adding an offset to the base…

Cortex-A7 Boot from SPI NOR: Understanding the Boot Process and XIP Limitations The Cortex-A7 processor, as part of the ARMv7-A architecture, is widely used in embedded systems due to its balance of performance and power efficiency. One common use case involves booting from external SPI NOR flash memory, which is a cost-effective and space-efficient solution…

Cortex-M4 and PSRAM Voltage Level Mismatch Challenges When interfacing an ARM Cortex-M4 microcontroller operating at 3.3V with a PSRAM (Pseudo Static Random Access Memory) device operating at 1.8V, voltage level compatibility becomes a critical concern. The Cortex-M4, a widely used 32-bit RISC processor, is often employed in embedded systems where memory interfacing is a common…

ARM Cortex-A53 Shareability Domains and Cache Coherency in Multi-Cluster Systems The ARM Cortex-A53 processor, a popular choice for embedded systems and mobile applications, is designed with a focus on power efficiency and performance. One of its key features is the support for multiple cache levels and shareability domains, which are critical for maintaining cache coherency…

ARM T32 IT Instruction: Purpose and Common Misunderstandings The ARM T32 (Thumb-2) instruction set includes the IT (If-Then) instruction, which is a powerful yet often misunderstood feature. The IT instruction is used to conditionally execute up to four subsequent instructions based on the state of the ARM condition flags. This capability is particularly useful in…

ARM Cortex-M4 Load/Store Instruction Offset Timing Anomalies The ARM Cortex-M4 processor, a widely used microcontroller core, exhibits a peculiar behavior when executing load and store instructions with specific offset values. This behavior manifests as unexpected variations in clock cycle consumption for offsets starting from 30 (decimal) and beyond. The anomaly is particularly noticeable when the…