Author: System on Chips

ARMv7-M Code Execution on ARMv8-M Non-Secure Mode The ARMv8-M architecture introduces significant enhancements over its predecessor, ARMv7-M, particularly in the areas of security and performance. One of the most frequently asked questions is whether code compiled for ARMv7-M can run unmodified on ARMv8-M, specifically in the non-secure mode. The ARMv8-M architecture is designed to be…

ARM Cortex-M4 Cycle Count Discrepancy in arm_dot_prod_q7 Function The ARM Cortex-M4 processor is widely used in embedded systems due to its balance of performance and power efficiency. One of the key features of the Cortex-M4 is its ability to execute Digital Signal Processing (DSP) instructions efficiently, which is crucial for applications such as audio processing,…

Secure Code Writing to Non-Secure Memory Without Retention In ARMv8-M architectures, a common issue arises when secure code attempts to write values to non-secure memory, only to find that the written values are not retained when accessed by non-secure code. This problem is particularly prevalent in systems where secure and non-secure states coexist, such as…

HSE Clock Source Behavior During Deep Sleep and Wake-Up When utilizing the High-Speed External (HSE) clock source on an STM32 Cortex-M4 microcontroller, entering deep sleep modes such as STOP or Standby can lead to unexpected behavior regarding the system clock source. During deep sleep, the HSE is typically turned off to conserve power, and upon…

ARM Cortex-M4 NVIC Priority Change During ISR Execution The ARM Cortex-M4 microcontroller, based on the ARMv7-M architecture, is designed to handle nested interrupts efficiently through its Nested Vectored Interrupt Controller (NVIC). However, a subtle yet critical issue arises when attempting to change the priority of a currently executing Interrupt Service Routine (ISR). This issue manifests…

ARM TrustZone Context Switch Overhead in Non-Secure and Secure Worlds The ARM TrustZone technology introduces a hardware-based security feature that partitions the system into secure and non-secure worlds. This partitioning is crucial for isolating sensitive operations and data from non-secure applications. However, this isolation comes with an overhead, particularly during context switches between the secure…

ARM Cortex-M4 IT Block Execution Behavior and Cycle Counting The ARM Cortex-M4 processor, like other ARM Cortex-M series processors, supports the Thumb-2 instruction set, which includes the IT (If-Then) instruction for conditional execution. The IT instruction allows up to four subsequent instructions to be conditionally executed based on the condition specified in the IT instruction….

ARMv8-A D-Cache Behavior When MMU is Disabled In ARMv8-A architectures, the relationship between the Memory Management Unit (MMU) and the Data Cache (D-Cache) is tightly coupled, and understanding this relationship is critical for optimizing system performance and ensuring correct functionality. When the MMU is disabled, the system treats all memory accesses as if they are…

Non-Secure Caller Identification Challenges in TrustZone Environments In ARM TrustZone-based systems, Non-Secure Call (NSC) functions provide a bridge for non-secure tasks to access secure services. However, a critical challenge arises when attempting to restrict NSC calls to specific Real-Time Operating System (RTOS) tasks. The secure side lacks inherent awareness of the calling task’s identity, as…

ARM Cortex-M4 Bootloader Stack Pointer Initialization and Interrupt Handling The core issue revolves around the improper initialization of the stack pointer and interrupt handling mechanisms when transitioning from a bootloader to the main application firmware on an ARM Cortex-M4 microcontroller. The bootloader is designed to update the firmware of a GD32E103 microcontroller, but after loading…