Author: System on Chips

Understanding Cortex-M33 Tracing: ETM, ETB, and MTB Interactions The Cortex-M33 processor, part of ARM’s Cortex-M series, is designed for embedded systems requiring high performance and security. One of its advanced features is its tracing capabilities, which are critical for debugging and performance analysis. The Embedded Trace Macrocell (ETM), Embedded Trace Buffer (ETB), and Micro Trace…

External Flash Selection and Integration with Cortex-M0 When integrating an ARM Cortex-M0 processor with external flash memory, the first step is selecting a compatible flash device. The Cortex-M0, being a low-power, 32-bit RISC processor, is often used in embedded systems where external flash memory is required for storing firmware or data. Commercial external flash memories,…

SPI Receiver Fails to Enable with SYNCBUSY.CTRLB Stuck High The issue at hand involves the SPI receiver on an ATSAMD21G18A (Cortex-M0) microcontroller failing to enable, with the SYNCBUSY.CTRLB bit persistently set to one. This prevents the receiver from being enabled, as indicated by the CTRLB.RXEN bit not being set correctly. The problem manifests after enabling…

UART Data Corruption with Dummy Characters in Nuvoton MS51FB9AE The issue described involves the reception of corrupted UART data on the Nuvoton MS51FB9AE microcontroller, which is based on the ARM Cortex-M architecture. The user reports that while testing a UART loopback program, dummy characters (e.g., "⸮") appear intermittently in the received data stream. For example,…

ARM VETX.32 Bitwise Rotate Performance Bottleneck on ARM7A The ARM VETX.32 instruction set includes specialized operations for vectorized bitwise manipulations, which are commonly used in embedded systems for tasks such as cryptography, signal processing, and data compression. One such operation is the in-place bitwise rotate, denoted as VETX.32 q1, q1, q1, #3, which rotates the…

Synchronous Data Abort and FIQ Timing in Cortex-R5F Memory Access In the ARM Cortex-R5F processor, a scenario can arise where a memory access operation, such as a read from L2 memory, triggers both a synchronous data abort and a Fast Interrupt Request (FIQ) nearly simultaneously. This situation is particularly observed when the memory subsystem is…

Cortex-M0 Vector Table Fetch Behavior and VTOR Absence The ARM Cortex-M0 processor, unlike its more advanced siblings such as the Cortex-M3, M4, and M7, does not feature a Vector Table Offset Register (VTOR). This architectural decision has significant implications for how the processor handles interrupt vectors. On the Cortex-M0, the vector table is always fetched…

Secure SPI Peripheral Activation Limitations on STM32MP157-DK1 The STM32MP157-DK1 development board, featuring an ARM Cortex-A processor with TrustZone security, presents a unique challenge when attempting to configure SPI peripherals for secure-side operations. Specifically, the board restricts secure-side SPI usage to SPI 6, which is not externally accessible. This limitation raises questions about the feasibility of…

ARM Cortex-M33 Secure to Non-Secure State Transition Challenges The ARM Cortex-M33 processor, part of the ARMv8-M architecture, introduces a robust security model that partitions the system into Secure and Non-Secure states. This partitioning is crucial for applications requiring high levels of security, such as IoT devices, where sensitive data and critical operations must be isolated…

STM32F103 SCU Peripheral Missing in Keil MDK-ARM Environment The STM32F103 microcontroller, based on the ARM Cortex-M3 architecture, is a popular choice for embedded systems development due to its balance of performance, power efficiency, and peripheral integration. However, when starting with this microcontroller, especially for those transitioning from other ARM-based platforms, there can be confusion regarding…