Author: System on Chips

Cortex-A35 SCU Arbitration and Core Interference in Multi-Core Clusters The Cortex-A35 processor, known for its power efficiency and scalability, is often deployed in multi-core configurations, such as the quad-core cluster found in the NXP i.MX8QX. One of the critical challenges in such configurations is understanding and managing the interference between cores, particularly when accessing shared…

NUMA Architecture in ARMv8: Core Concepts and Hardware Requirements Non-Uniform Memory Access (NUMA) is a memory design architecture used in multiprocessing systems where memory access times depend on the memory location relative to the processor. In ARMv8 architecture, NUMA support is not inherently provided by the ARM cores themselves but is instead implemented at the…

ARM Musca A1 Memory Bandwidth Profiling Challenges The ARM Musca A1 is a resource-constrained embedded development board featuring a dual-core ARM Cortex-M33 processor and three distinct memory types: 8 MB of FLASH memory, 2 MB of eSRAM, and 128 KB of iSRAM. Profiling memory bandwidth on such a system presents unique challenges due to the…

Cortex A9 ACP Slave Outstanding Read Request Handling The Cortex A9 Accelerator Coherency Port (ACP) is a critical interface for enabling efficient data sharing between the processor and external accelerators or DMA engines. The ACP allows these external agents to access the Cortex A9’s cache-coherent memory subsystem, ensuring data consistency without requiring explicit cache maintenance…

Cortex-A9 MMU Configuration and Data Abort on Unaligned Access The core issue revolves around a baremetal application running on a Cortex-A9 processor that encounters a data abort when the Memory Management Unit (MMU) is enabled. The application executes successfully in a debugger environment but fails when executed directly on the hardware, specifically when the MMU…

ARM CCI-550 Snoop Filter Sizing and Configuration Challenges The ARM CoreLink Cache Coherent Interconnect (CCI) 550 is a critical component in modern ARM-based systems, particularly in Big.LITTLE configurations where multiple clusters of processors with varying cache sizes must maintain coherence. The snoop filter in the CCI-550 plays a pivotal role in reducing unnecessary snoop traffic…

Cortex-M7 Interrupt Latency: 12 vs. 14 Clock Cycles The Cortex-M7 processor, like other members of the Cortex-M family, is designed for deterministic real-time performance. One of the key metrics for real-time systems is interrupt latency, which is the time between the occurrence of an interrupt and the start of the interrupt handler. For the Cortex-M7,…

ARM Cortex-M33 Multicore Debug Resource Allocation and Sharing The ARM Cortex-M33 is a powerful microcontroller core designed for embedded systems, particularly those requiring security and real-time performance. One of the key challenges when working with multicore systems based on the Cortex-M33 is understanding how debug resources are allocated and shared between cores. Unlike single-core systems,…

Cortex-A5 Speculative Loads on Uninitialized Normal Memory Regions The Cortex-A5 processor, despite being an in-order execution architecture, is capable of performing speculative loads and prefetching data from memory regions marked as Normal and cacheable. This behavior can lead to unintended memory access attempts, especially when the memory subsystem is not fully initialized or ready. In…

ARM Cortex-M7 SVCall Handler Misbehavior and Hard Fault Escalation The issue at hand involves an ARM Cortex-M7 processor (specifically the NXP i.MX RT1062 chip) where the SVCall (Supervisor Call) handler is misbehaving, resulting in either a return to an invalid address (0xdeadbeee) or escalation to a Hard Fault. The problem manifests during runtime but does…