AXI4 Narrow Transfer Misalignment in 64-bit to 32-bit Bus Conversion

The core issue revolves around the misalignment and incorrect handling of the AXI4 WSTRB (Write Strobe) signal during narrow transfers from a 64-bit master to a 32-bit slave. The master is configured to perform a burst transfer with specific AWLEN, AWSIZE, and AWBURST settings, but the slave fails to correctly receive the data when certain WSTRB patterns are used. This problem is particularly evident when the master attempts to send data in non-sequential byte lanes, such as WSTRB = 0x03, 0x30, 0xC0, 0x0C, which do not align with the AXI4 protocol’s rules for narrow transfers.

The AXI4 protocol mandates that the WSTRB signal must align with the address (AWADDR), burst type (AWBURST), and transfer size (AWSIZE). In this case, the master is configured with AWSIZE = 0x1 (16-bit transfers), which restricts the valid WSTRB patterns to specific byte lanes for each transfer in the burst. However, the master is generating WSTRB patterns that violate these rules, leading to data misalignment and incorrect reception at the slave.

The issue is further complicated by the 64-bit to 32-bit bus conversion. The master’s 64-bit data bus must be split into two 32-bit chunks for the slave, but the WSTRB patterns must also be correctly mapped to the slave’s 32-bit bus. The current implementation fails to properly handle this mapping, especially when the master attempts to send data in non-sequential byte lanes or when the WSTRB patterns do not follow the expected sequence (e.g., sending WSTRB = 0xF0 before WSTRB = 0x0F).

AXI4 Protocol Violations and Narrow Transfer Constraints

The root cause of the issue lies in the violation of the AXI4 protocol’s rules for narrow transfers and the incorrect handling of the WSTRB signal during 64-bit to 32-bit bus conversion. The AXI4 protocol specifies that the WSTRB signal must align with the address (AWADDR), burst type (AWBURST), and transfer size (AWSIZE). In this case, the master is configured with AWSIZE = 0x1 (16-bit transfers), which restricts the valid WSTRB patterns to specific byte lanes for each transfer in the burst.

For example, in a 64-bit master with AWSIZE = 0x1, the first transfer must use WSTRB[1:0], the second transfer must use WSTRB[3:2], the third transfer must use WSTRB[5:4], and the fourth transfer must use WSTRB[7:6]. However, the master is generating WSTRB patterns that violate these rules, such as WSTRB = 0x03, 0x30, 0xC0, 0x0C, which attempt to use byte lanes that are not aligned with the AWSIZE setting.

Additionally, the 64-bit to 32-bit bus conversion logic is not correctly mapping the WSTRB patterns from the master to the slave. The slave expects the WSTRB signal to align with its 32-bit data bus, but the current implementation is not properly handling the mapping of the master’s WSTRB patterns to the slave’s WSTRB signal. This results in data misalignment and incorrect reception at the slave.

The issue is further exacerbated by the master’s attempt to send data in non-sequential byte lanes, such as WSTRB = 0xF0 followed by WSTRB = 0x0F. According to the AXI4 protocol, the WSTRB patterns must follow a specific sequence based on the AWADDR and AWSIZE settings. If the start address ends with 0x0 or 0x8, the lower half of the data bus should be used for the first transfer, and the WSTRB pattern should be 0x0F followed by 0xF0. Conversely, if the start address ends with 0x4 or 0xC, the upper half of the data bus should be used for the first transfer, and the WSTRB pattern should be 0xF0 followed by 0x0F. The current implementation does not adhere to these rules, leading to data transfer errors.

Correcting AXI4 Narrow Transfer and WSTRB Handling

To resolve the issue, the AXI4 master must be configured to adhere to the protocol’s rules for narrow transfers and the WSTRB signal. The following steps outline the necessary corrections:

  1. Align WSTRB with AWSIZE and AWADDR: The master must ensure that the WSTRB signal aligns with the AWSIZE and AWADDR settings. For a 64-bit master with AWSIZE = 0x1 (16-bit transfers), the valid WSTRB patterns for each transfer in the burst are as follows:

    • First transfer: WSTRB[1:0] (e.g., 0x03, 0x02, 0x01, 0x00)
    • Second transfer: WSTRB[3:2] (e.g., 0x0C, 0x08, 0x04, 0x00)
    • Third transfer: WSTRB[5:4] (e.g., 0x30, 0x20, 0x10, 0x00)
    • Fourth transfer: WSTRB[7:6] (e.g., 0xC0, 0x80, 0x40, 0x00)

    The master must generate WSTRB patterns that adhere to these constraints, ensuring that only the specified byte lanes are used for each transfer.

  2. Correct 64-bit to 32-bit WSTRB Mapping: The 64-bit to 32-bit bus conversion logic must correctly map the master’s WSTRB patterns to the slave’s WSTRB signal. The slave’s WSTRB signal should align with its 32-bit data bus, and the conversion logic must ensure that the correct byte lanes are activated based on the master’s WSTRB patterns.

    For example, if the master’s WSTRB pattern is 0x03 (activating WSTRB[1:0]), the slave’s WSTRB pattern should be 0x03 (activating WSTRB[1:0]). Similarly, if the master’s WSTRB pattern is 0x0C (activating WSTRB[3:2]), the slave’s WSTRB pattern should be 0x0C (activating WSTRB[3:2]).

  3. Sequential WSTRB Pattern Generation: The master must generate WSTRB patterns in the correct sequence based on the AWADDR and AWSIZE settings. If the start address ends with 0x0 or 0x8, the master should first activate the lower half of the data bus (WSTRB = 0x0F) followed by the upper half (WSTRB = 0xF0). Conversely, if the start address ends with 0x4 or 0xC, the master should first activate the upper half of the data bus (WSTRB = 0xF0) followed by the lower half (WSTRB = 0x0F).

    This ensures that the data is correctly aligned with the slave’s 32-bit data bus and that the WSTRB patterns follow the AXI4 protocol’s rules for narrow transfers.

  4. Verification and Testing: The corrected implementation must be thoroughly verified to ensure that the WSTRB patterns are correctly generated and mapped during 64-bit to 32-bit bus conversion. This includes testing various combinations of AWADDR, AWSIZE, AWLEN, and AWBURST settings to ensure that the data is correctly transferred to the slave.

    The verification process should also include corner cases, such as non-sequential WSTRB patterns and different start addresses, to ensure that the implementation adheres to the AXI4 protocol’s rules for narrow transfers.

By following these steps, the AXI4 master can be configured to correctly handle narrow transfers and the WSTRB signal during 64-bit to 32-bit bus conversion, ensuring that the data is correctly aligned and received by the slave.

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