Architectures and Processors

CMN700 Register Read Requests Not Serviced by CMN700 Directly The core issue revolves around the inability of an ARM N1 core to successfully read a CMN700 register in a FastModel simulation environment. The ARM N1 core initiates a read request targeting a CMN700 register at address 0x42d1d80, but the request is not serviced directly by…

Qualcomm Snapdragon Datasheet Accessibility Challenges The Qualcomm Snapdragon 8cx Gen 3 and Qualcomm Snapdragon 7c Gen 2 SC7180P are highly specialized system-on-chip (SoC) platforms designed for advanced computing and mobile applications. These SoCs integrate ARM-based architectures with Qualcomm’s proprietary technologies, making them powerful yet complex to work with. One of the primary challenges faced by…

Understanding the Socrates Workspace Structure and Dependencies The Socrates workspace is a critical component in ARM-based SoC design, serving as the central repository for project configurations, simulation environments, and tool settings. A typical Socrates workspace contains several key directories and files that maintain intricate relationships with both the local filesystem and the ARM toolchain. The…

ARESETn and BRESETn Asynchrony Causing Unexpected Data Transfer in NIC400 When designing a system using the ARM NIC400 interconnect with multiple clock domains, one of the critical challenges is managing the reset sequence for asynchronous FIFOs that bridge these domains. In this scenario, the system employs two clock domains: ACLK and BCLK. The NIC400 connects…

Cortex-A53 AXI Read Signal Anomalies with Non-Cacheable Memory The issue revolves around unexpected behavior in the AXI read signals when accessing non-cacheable memory regions on a Kria KV260 board with a Cortex-A53 processor. Specifically, the AXI read transactions exhibit discrepancies in signal values, such as ARSIZE and ARLEN, when compared to the expected behavior for…

AXI4 Initiator-Target Data Misalignment During Narrow Burst Transfers In an AXI4-based system, narrow burst transfers occur when the data width of the transaction is smaller than the width of the data bus. For instance, a 32-bit read request on a 64-bit data bus is a narrow burst transfer. The AXI protocol specifies that the data…

ARMv8-A FVP SMMUv3 Device Integration and Request Simulation Challenges SMMUv3 Device Integration and Request Simulation in ARMv8-A FVP The integration of devices behind the System Memory Management Unit version 3 (SMMUv3) in an ARMv8-A Fixed Virtual Platform (FVP) presents a complex challenge, particularly when attempting to simulate device requests through the SMMUv3. The SMMUv3 is…

AWLEN Signal Optionality in AXI4 Masters and Its Implications for Slaves The AWLEN signal in the AXI4 protocol is a critical component of the write address channel, responsible for indicating the number of data transfers in a burst transaction. The AXI4 specification describes AWLEN as optional for masters but mandatory for slaves, which raises questions…

NIC-400 Reset Timing Challenges in Long-Distance SoC Implementations In complex System-on-Chip (SoC) designs utilizing ARM’s NIC-400 interconnect, one of the critical challenges is ensuring proper reset signal distribution across long physical distances. The NIC-400 interconnect, being a highly configurable network-on-chip (NoC) solution, often spans large sections of the SoC to connect multiple IP blocks, memory…

PL011 UART Interrupts Not Triggering in ARMv8-R AArch32 Mode When running Zephyr on an ARMv8-R AEM FVP in AArch32 mode, the PL011 UART interrupts are not being triggered. This issue can stem from multiple factors, including incorrect configuration of the PL011 UART peripheral, misalignment in the interrupt controller setup, or issues with the Zephyr OS…