Architectures and Processors

ARM Cortex-M0+ WFI Instruction Ignored During Deep Sleep Mode Issue Overview The ARM Cortex-M0+ processor, specifically the STM32L051 microcontroller, is occasionally ignoring the Wait For Interrupt (WFI) instruction when attempting to enter deep sleep mode. This issue manifests as the processor failing to enter the low-power state and instead continuing to execute code, which defeats…

ARM Cortex-A53 ACP Burst Size Constraints and DMA Behavior The ARM Cortex-A53 processor, part of the ARMv8-A architecture, is widely used in embedded systems due to its balance of performance and power efficiency. One of its key features is the Accelerator Coherency Port (ACP), which allows external devices, such as DMA controllers, to access the…

ARMv8-A MRS CPSR/APSR Instruction Latency and Its Impact on Real-Time Systems The MRS (Move to Register from System Register) instruction in ARMv8-A architectures is a critical operation for reading system registers such as the Current Program Status Register (CPSR) or the Application Program Status Register (APSR). Understanding the latency of this instruction is essential for…

ARM TrustZone Secure-Normal World Transition Latency The ARM TrustZone technology provides a robust security framework by partitioning the system into two distinct worlds: the Secure World and the Normal World. This partitioning allows sensitive operations to be isolated from the rest of the system, thereby enhancing security. However, the transition between these two worlds is…

ARMv7 Secure and Non-Secure Mode Stack Pointer Configuration Challenges The ARMv7 architecture introduces the concept of Secure and Non-Secure states, which are designed to provide isolation between trusted (Secure) and untrusted (Non-Secure) execution environments. This separation is crucial for systems that require robust security, such as those implementing TrustZone technology. One of the key challenges…

ARMv8.1-A Access Flag Hardware Management Overview The ARMv8.1-A architecture introduces a significant enhancement in the management of the Access Flag (AF) through hardware. Traditionally, the Access Flag in page table entries was managed by software, requiring explicit intervention from the operating system or firmware to update the flag when a memory page or section was…

ARM Cortex-A72 Memory Access Tracing Limitations The ARM Cortex-A72 processor, a high-performance core within the ARMv8-A architecture, is widely used in applications requiring significant computational power, such as mobile devices, networking equipment, and embedded systems. However, one of the notable limitations of the Cortex-A72 is its lack of support for data access tracing through Embedded…

ARMv7-A MSR Instruction Format and Bracket Notation The ARMv7-A architecture documentation uses a specific notation to describe the encoding of instructions, including the use of brackets in the bitfield descriptions. In the case of the MSR (Move to System Register) instruction, the bit indices from 12 to 15 are marked with brackets, indicating a special…

Thumb-2 Instruction Width Selection and External Reference Challenges The Thumb-2 instruction set, introduced by ARM, combines 16-bit and 32-bit instructions to provide a balance between code density and performance. One of the key challenges when working with Thumb-2 is understanding when and why to explicitly specify the width of an instruction using the .W suffix….

Cortex-M3 and PrimeCell uDMAC Bus Arbitration in TI CC2640R2F The integration of the ARM Cortex-M3 microcontroller and the PrimeCell uDMAC (Micro Direct Memory Access Controller) in the Texas Instruments CC2640R2F Bluetooth controller presents a complex scenario where bus arbitration between the two masters can lead to performance bottlenecks. The Cortex-M3 and the uDMAC both operate…