Architectures and Processors

ARM Cortex-A Cache Coherency and Memory Access Latency in EL3 vs NS.EL1 The performance discrepancy of memcpy() between EL3 (ARM Trusted Firmware BL31) and NS.EL1 (Linux kernel module) is primarily rooted in the differences in cache coherency models, memory access latencies, and privilege level overheads. In NS.EL1, the Linux kernel operates in a non-secure state…

ARM FVP SMMU Peripheral Emulation and Testing Challenges The ARM Fixed Virtual Platform (FVP) is a powerful tool for simulating ARM-based systems, enabling developers to test software and hardware interactions without requiring physical hardware. However, when it comes to testing peripherals connected through the System Memory Management Unit (SMMU), particularly in the context of emulating…

Cortex-A53 BUS_ACCESS Event Underreporting and Read Allocate Mode Writes The Cortex-A53 Performance Monitoring Unit (PMU) provides a suite of events that allow developers to profile and analyze system performance. One such event, BUS_ACCESS (event ID 0x19), is designed to count all bus accesses, including cacheable traffic, non-cacheable traffic, and write streaming. However, as noted in…

ARM TrustZone Peripheral Access Mechanisms and Security Models The ARM TrustZone architecture introduces a hardware-based security model that partitions the system into Secure World (SW) and Non-Secure World (NW). This partitioning extends to peripherals, which can be accessed by either world depending on their configuration and the security requirements of the system. The core issue…

Understanding ADC Channel Reading and Serial Output on ARM Cortex-M3 The process of reading an ADC channel and printing its value to a serial terminal on an ARM Cortex-M3 microcontroller, such as the ATSAM3X8E, involves several critical steps. These steps include configuring the ADC peripheral, setting up the UART for serial communication, and ensuring proper…

L2 Cache Stalls Due to Indefinite Memory Read Issues The ARM Cortex-A series processors are widely used in embedded systems due to their high performance and efficiency. However, certain architectural nuances can lead to unexpected behavior, particularly in the memory subsystem. One such issue is the indefinite stalling of memory reads in the L2 cache,…

ARM CHI Protocol Cache Line States and the EMPTY State The ARM Coherent Hub Interface (CHI) protocol is a critical component of ARM’s advanced cache coherency framework, designed to manage data consistency across multiple cores, caches, and memory subsystems in complex System-on-Chip (SoC) designs. One of the key features of the CHI protocol is its…

ARM Cortex-R52 AXI4/128-bit Memory Interface Challenges The ARM Cortex-R52 processor, designed for real-time and safety-critical applications, features an AXI4/128-bit memory interface. This interface is crucial for achieving high bandwidth and low latency in data-intensive applications. However, integrating 128-bit memories with the Cortex-R52 can present challenges, particularly when attempting to leverage existing Intellectual Property (IP) blocks…

PL310 L2 Cache Controller RAM Initialization Overview The PL310 L2 Cache Controller, a critical component in ARM-based systems, utilizes two primary types of RAM: Data RAM and Tag RAM. These RAMs are integral to the cache’s operation, storing cached data and metadata, respectively. A common question arises regarding the initialization of these RAMs, particularly when…

ARM Cortex-A Series Instruction Reordering and System Register Synchronization In ARM AArch64 architectures, particularly in the Cortex-A series, the processor’s out-of-order execution capabilities can lead to subtle issues when dealing with system registers and memory operations. The specific scenario involves ensuring that a write to the Performance Monitors Control Register (PMCR_EL0) is completed before a…