ARM Neoverse N1 Pipeline Behavior: Adds with LSL >4 Using I Pipeline Instead of M Pipeline
ARM Cortex-M4 Cache Coherency Problems During DMA Transfers The Neoverse N1 microarchitecture, a high-performance ARM core designed for server and infrastructure workloads, exhibits unexpected pipeline behavior when executing specific arithmetic instructions with large shift values. Specifically, the adds instruction with a logical shift left (LSL) greater than 4, such as adds x3, x4, x5, lsl…