Architectures and Processors

Full Adder Output Delay Discrepancy During Simultaneous Input Transitions The issue revolves around the behavior of the full adder cell from the ARM standard library during timing simulations. Specifically, the output delay of the carry-out signal (CO) exhibits inconsistent behavior depending on the timing of the input transitions. When the inputs A and B fall…

AXI WRAP Burst Addressing Mechanics and Misconceptions The AXI (Advanced eXtensible Interface) protocol is a cornerstone of modern ARM-based SoC designs, providing a robust framework for high-performance data transfers between components. One of the more nuanced aspects of AXI is the WRAP burst type, which is often misunderstood due to its unique addressing behavior. The…

ARM PL081 DMA Controller Transfer Limitation to 256 Bytes per Burst The issue revolves around the ARM PL081 DMA controller’s inability to transfer the full 16KB of data from a custom peripheral to a memory buffer. The DMA controller is configured to transfer data in bursts of 256 bytes, but the transfer stops after completing…

ARM Freezes When Accessing FPGA DDR Memory via H2F_AXI Bus In a system where an ARM processor is interfaced with an FPGA through an AXI bus, a critical issue arises where the ARM freezes completely when attempting to access the FPGA’s DDR memory. The system configuration includes an ARM processor running Linux, an FPGA handling…

AHB Protocol Constraints on HWDATA and HRDATA Usage The Advanced High-performance Bus (AHB) protocol, part of the ARM AMBA (Advanced Microcontroller Bus Architecture) family, is designed to facilitate efficient data transfers between masters and slaves in a system-on-chip (SoC). A critical aspect of the AHB protocol is its handling of data buses, specifically the HWDATA…

AXI 4 Upsizer/Downsizer WSTRB Misalignment During 256-bit to 128-bit Data Width Conversion The core issue revolves around a protocol checker error flagged during the conversion of a 256-bit AXI transaction into two 128-bit transactions targeting two separate slaves. The error message, "Write strobes must only be asserted for the correct byte lanes as determined from…

APB Slave Sampling of Address and Data Signals During Setup and Access Phases The Advanced Peripheral Bus (APB) protocol, part of the ARM AMBA (Advanced Microcontroller Bus Architecture) family, is a simple yet robust interface for connecting low-bandwidth peripherals to a system-on-chip (SoC). A common challenge in APB-based designs is determining the correct timing for…

GICv3 Stream Protocol: Interrupt Retrieval from CPU Interface During 1-of-N SPI Configuration The ARM Generic Interrupt Controller version 3 (GICv3) is a critical component in modern ARM-based SoCs, responsible for managing and distributing interrupts across multiple processing elements (PEs). One of the advanced features of GICv3 is the Stream Protocol, which governs how interrupts are…

Cortex-R52 Clock Gate Challenges in FPGA Prototyping The Cortex-R52, a high-performance real-time processor from ARM, is widely used in safety-critical and real-time applications. Its architecture includes multiple clock gates to manage power consumption effectively. However, during FPGA prototyping, these clock gates can introduce significant challenges, particularly when it comes to timing closure. The primary issue…

AXI Unaligned Transfer Mechanics and WDATA Bit Utilization In the context of ARM’s Advanced eXtensible Interface (AXI) protocol, unaligned transfers present a unique set of challenges and considerations, particularly concerning the utilization of the WDATA signal bits. An unaligned transfer occurs when the starting address of a data transfer does not align with the natural…