Architectures and Processors

Custom Accelerator Integration Challenges with ARM CoreLink CMN-600 Integrating a custom accelerator with ARM CoreLink CMN-600 using the CHI (Coherent Hub Interface) or ACE-Lite (AXI Coherency Extensions Lite) interface presents several technical challenges. The CoreLink CMN-600 is a highly configurable interconnect designed for high-performance SoCs, supporting both coherent and non-coherent transactions. The CHI protocol is…

ARM Cryptocell 310 Side Channel Attack Vulnerabilities The ARM Cryptocell 310 is a hardware-based security subsystem designed to provide cryptographic operations and secure key storage for ARM-based SoCs. One of the critical concerns in cryptographic implementations is protection against side channel attacks, particularly timing analysis and differential power analysis (DPA). Timing analysis exploits variations in…

Byte Invariance in AXI: Definition and Functional Significance Byte invariance is a fundamental concept in the AXI (Advanced eXtensible Interface) protocol, which is widely used in ARM-based SoC designs. It refers to the property that ensures data bytes are mapped to the same byte lanes on the data bus, regardless of the system’s endianness. This…

APB 2.0 Continuous Transfer Protocol and State Transition Requirements The Advanced Peripheral Bus (APB) 2.0 protocol is a low-cost, low-power interface designed for peripheral communication in ARM-based SoCs. It is a part of the AMBA (Advanced Microcontroller Bus Architecture) family and is widely used for connecting low-bandwidth peripherals. A key feature of APB 2.0 is…

Full Adder Output Delay Discrepancy During Simultaneous Input Transitions The issue revolves around the behavior of the full adder cell from the ARM standard library during timing simulations. Specifically, the output delay of the carry-out signal (CO) exhibits inconsistent behavior depending on the timing of the input transitions. When the inputs A and B fall…

AXI WRAP Burst Addressing Mechanics and Misconceptions The AXI (Advanced eXtensible Interface) protocol is a cornerstone of modern ARM-based SoC designs, providing a robust framework for high-performance data transfers between components. One of the more nuanced aspects of AXI is the WRAP burst type, which is often misunderstood due to its unique addressing behavior. The…

ARM PL081 DMA Controller Transfer Limitation to 256 Bytes per Burst The issue revolves around the ARM PL081 DMA controller’s inability to transfer the full 16KB of data from a custom peripheral to a memory buffer. The DMA controller is configured to transfer data in bursts of 256 bytes, but the transfer stops after completing…

ARM Freezes When Accessing FPGA DDR Memory via H2F_AXI Bus In a system where an ARM processor is interfaced with an FPGA through an AXI bus, a critical issue arises where the ARM freezes completely when attempting to access the FPGA’s DDR memory. The system configuration includes an ARM processor running Linux, an FPGA handling…

AHB Protocol Constraints on HWDATA and HRDATA Usage The Advanced High-performance Bus (AHB) protocol, part of the ARM AMBA (Advanced Microcontroller Bus Architecture) family, is designed to facilitate efficient data transfers between masters and slaves in a system-on-chip (SoC). A critical aspect of the AHB protocol is its handling of data buses, specifically the HWDATA…

AXI 4 Upsizer/Downsizer WSTRB Misalignment During 256-bit to 128-bit Data Width Conversion The core issue revolves around a protocol checker error flagged during the conversion of a 256-bit AXI transaction into two 128-bit transactions targeting two separate slaves. The error message, "Write strobes must only be asserted for the correct byte lanes as determined from…