ARM Cortex-M3 Exclusive Access Issues: LDREX/STREX vs LDR/STR on AXI and AHB-Lite Buses
ARM Cortex-M3 Exclusive Access Failing on AXI and AHB-Lite Buses The core issue revolves around the incorrect behavior of exclusive access instructions (LDREX/STREX) on an ARM Cortex-M3-based SoC design. The design integrates a Cortex-M3 processor with a custom AHB-Lite to AXI3 bridge, similar to the Xilinx DesignStart platform. The processor boots correctly and executes instructions,…