Architectures and Processors

ARM Cortex-A9 Dual-Core AMP Baremetal Execution Issues The challenge of configuring an Asymmetric Multiprocessing (AMP) baremetal environment on an ARM Cortex-A9 dual-core SoC, such as the one found in the Terasic DE1-SoC, involves running two separate binaries on each core independently. This setup requires careful handling of core initialization, binary loading, and synchronization to ensure…

SSL Handshake Exception During CMSIS Pack Download The issue at hand involves a failure in the SSL handshake process when attempting to download the CMSIS pack using ARM Development Studio 2020.0. The specific error message is javax.net.ssl.SSLHandshakeException: PKIX path building failed: sun.security.provider.certpath.SunCertPathBuilderException: unable to find valid certification path to requested target. This error indicates that…

ARM Base FVP Debugging Challenges with GDB Integration Debugging ARM-based systems using the ARM Base Fixed Virtual Platform (FVP) can be a complex task, especially when integrating third-party tools like GDB. The ARM Base FVP is a cycle-accurate simulation model that emulates ARM-based SoCs, allowing developers to test and debug their software and hardware designs…

AXI ID Width Mismatch in Dual-System ARM Cortex-A15 and Cortex-R7 Integration When integrating two independent ARM-based systems, such as a Cortex-A15 and a Cortex-R7, each operating on separate AXI buses, a common challenge arises when attempting to interconnect these systems for mutual access. The primary issue stems from the AXI ID width configuration, which is…

ARM FVP Fails to Initialize Graphics Due to libGL Driver Issues The ARM Fixed Virtual Platform (FVP) is a critical tool for simulating ARM-based SoCs, enabling developers to test and validate their designs before hardware availability. However, when running the FVP_MPS2_Cortex-M55 model on an unsupported Linux distribution such as Manjaro, users may encounter libGL errors…

AMBA AHB SPLIT and RETRY Response Mechanisms The AMBA AHB (Advanced Microcontroller Bus Architecture Advanced High-performance Bus) protocol is a critical component in many ARM-based SoC designs. It facilitates communication between masters (such as CPUs, DMAs, etc.) and slaves (such as memory controllers, peripherals, etc.) over a shared bus. One of the key features of…

ARMv8 Top-Byte Ignore (TBI) Mechanism and Its Role in Address Translation The ARMv8 architecture introduces a feature called Top-Byte Ignore (TBI), which allows the top byte of a virtual address to be ignored during address translation. This feature is particularly useful in scenarios where the upper bits of an address are used for metadata or…

Cortex-M3 DesignStart DSM Simulation License Activation Failure When attempting to simulate the ARM Cortex-M3 DesignStart evaluation package using the DSM (Design Simulation Model) option enabled (DSM=yes), users often encounter license-related errors that prevent the simulation from running. This issue typically manifests as a failure to validate the Cortex-M3 Cycle Model license, even when the simulation…

AHB Arbiter Grant Timing and Master Behavior for Single Transfers In ARM AMBA AHB (Advanced High-performance Bus) systems, the interaction between the arbiter and bus masters is critical for efficient bus utilization and correct protocol compliance. A common scenario arises when a bus master requests the bus to perform only a single transfer. The AHB…

ARM Base FVP Freezing During Extended Idle Periods The ARM Base Fixed Virtual Platform (FVP) is a critical tool for simulating ARM-based SoCs, enabling developers to test and debug their designs before committing to silicon. However, a recurring issue has been observed where the FVP freezes after being left idle for approximately one hour. This…