ARM SoC Simulation Challenges with Mixed Abstraction Levels The design and verification of ARM-based System-on-Chip (SoC) architectures often require simulation environments that can handle multiple abstraction levels. Traditional simulation methods, such as Fast Models, rely on virtual models written in high-level languages like C/C++ or SystemC. While these models are efficient for early-stage development and…
ARMv8-R Hypervisor Trap to EL2 with Missing HSR.ISS Data During STRD Emulation In ARMv8-R AEM FVP platforms running in hypervisor mode (EL2) with a 32-bit guest (AArch32), a specific issue arises when emulating an MMIO region accessed by a guest using the STRD (Store Doubleword) instruction. The guest attempts to access a memory region protected…
NIC-400 AHB-Lite Protocol Constraints and AHB-FULL Feature Requirements The NIC-400 interconnect from ARM is a highly configurable network interconnect designed to support a variety of AMBA protocols, including AXI, AHB, and APB. However, it is important to note that the NIC-400 specifically supports the AHB-Lite protocol, which is a simplified version of the full AHB…
ARM CHI ReadClean Transaction Cache State Discrepancy Between Tables 4-5 and 4-33 The ARM Coherent Hub Interface (CHI) specification defines the behavior of cache states and transactions in a coherent system. A critical discrepancy exists between Table 4-5 and Table 4-33 regarding the permissible cache states for a ReadClean transaction. Table 4-5 suggests that only…
ARM AArch64 Memory Simulation Challenges on Windows 7 When embarking on the study of ARM AArch64 memory architecture, selecting the appropriate simulation tool is crucial. The primary challenge lies in the compatibility and functionality of available tools, especially when operating on older Windows platforms like Windows 7. ARM Developer Suite (ADS) 1.2, a legacy tool,…
ARM CHI Protocol Snoop Transactions and Their Role in Coherency The ARM Coherent Hub Interface (CHI) protocol is a critical component in modern ARM-based SoCs, enabling efficient communication between various request nodes (RNs) and the interconnect. One of the key aspects of CHI is its handling of snoop transactions, which are essential for maintaining cache…
Master AHB Lite to AHB5 Slave Connectivity and Addressing Misalignment The core issue revolves around the integration of a Master AHB Lite interface with an AHB5 Slave, specifically when attempting to bridge AHB5 to AXI5 for FPGA testing. The primary challenge lies in the misalignment of address spaces between the MicroBlaze processor and the AHB5_AXI5…
ARMv9 RME Support in Fast Models FVP: Missing Configuration Parameters The Realm Management Extension (RME) is a critical feature introduced in ARMv9 architectures, designed to enhance security by providing hardware-enforced isolation between different execution environments, such as Normal, Secure, and Realm worlds. Fast Models Fixed Virtual Platforms (FVPs) are widely used for pre-silicon development and…
CHI Device Memory Type Byte Access Behavior and Boundary Crossing In ARM’s Coherent Hub Interface (CHI) protocol, the handling of "Device" memory type transactions presents unique challenges, particularly when the transaction size exceeds the natural alignment boundary of the address space. Unlike "Normal" memory type transactions, which can wrap around address boundaries seamlessly, "Device" memory…
Inaccurate Timing Measurements with ARM Cortex-M4 DWT_CYCCNT on FVP When benchmarking code on the FVP_MPS2_Cortex-M4 simulator, one of the primary challenges is obtaining accurate timing measurements. The ARM Cortex-M4 processor provides a Data Watchpoint and Trace (DWT) unit, which includes a cycle counter (DWT_CYCCNT) that can be used to measure the number of clock cycles…