Cortex-A55 Performance Monitoring Unit (PMU) Counter Access Issues
The Cortex-A55, a high-efficiency CPU in ARM’s DynamIQ family, incorporates a Performance Monitoring Unit (PMU) that provides critical insights into system performance through hardware counters. These counters track events such as cache misses, branch mispredictions, and instruction execution cycles, enabling developers to identify bottlenecks and optimize software. However, accessing and configuring these PMU counters can be challenging, particularly when using third-party tools like PAPI (Performance Application Programming Interface) or frameworks such as perfmon2. The Cortex-A55’s PMU architecture, while similar to its predecessors like the Cortex-A53, introduces subtle differences in register configurations and event mappings that can lead to compatibility issues with existing tools. This post delves into the technical intricacies of accessing Cortex-A55 PMU counters, explores the root causes of these challenges, and provides detailed solutions for enabling PMU functionality.
PMU Register Mismatch and Tool Compatibility Limitations
The primary issue preventing access to Cortex-A55 PMU counters lies in the mismatch between the PMU register configurations expected by existing tools and the actual implementation in the Cortex-A55. Tools like PAPI and perfmon2 rely on predefined configuration files that map specific events to PMU registers. These files are typically tailored for older ARM cores, such as the Cortex-A53, and do not account for the Cortex-A55’s updated PMU architecture. For instance, the Cortex-A55 introduces new performance events and modifies the encoding of certain registers, rendering the default configuration files ineffective.
Additionally, the Cortex-A55’s PMU operates within ARM’s ARMv8.2-A architecture, which introduces enhancements to the PMU, such as extended event counters and improved filtering capabilities. These architectural changes necessitate updates to the software tools to ensure compatibility. Without these updates, attempts to access PMU counters may result in errors or incorrect data. Furthermore, the lack of documentation or community resources for extending these tools to support the Cortex-A55 exacerbates the problem, leaving developers to reverse-engineer the necessary configurations.
Another contributing factor is the reliance on kernel-level support for PMU access. The Linux kernel, for example, provides a perf subsystem that abstracts PMU access for user-space applications. However, the kernel’s perf subsystem must be explicitly configured to recognize the Cortex-A55’s PMU registers. If the kernel lacks this support, user-space tools like PAPI will fail to access the counters, even if the underlying hardware is functional.
Extending Tool Support and Direct PMU Register Access
To address the challenges of accessing Cortex-A55 PMU counters, developers can adopt a two-pronged approach: extending existing tool support and directly accessing PMU registers through custom code. Both methods require a deep understanding of the Cortex-A55’s PMU architecture and careful implementation to ensure accurate performance monitoring.
Extending Tool Support
The first step in extending tool support is to create or modify configuration files for the Cortex-A55. This involves mapping the Cortex-A55’s PMU events to the corresponding registers and updating the tool’s event definitions. For example, in the case of perfmon2, developers can use the Cortex-A53 configuration files as a baseline and replace the relevant parameters with values from the Cortex-A55 Technical Reference Manual (TRM). The TRM provides detailed information on the PMU registers, including their addresses, bit fields, and event encodings.
Once the configuration files are updated, the tool must be recompiled to incorporate the changes. This process may require modifications to the tool’s source code, particularly if it includes hardcoded assumptions about the PMU architecture. For instance, if the tool expects a specific number of counters or a particular event encoding, these assumptions must be revised to align with the Cortex-A55’s implementation.
After updating the tool, developers should verify its functionality by running test cases that exercise the PMU counters. This validation step is crucial to ensure that the tool accurately captures performance data and that the configuration changes do not introduce unintended side effects.
Direct PMU Register Access
For developers who prefer a more hands-on approach, directly accessing the Cortex-A55’s PMU registers through custom code provides greater control and flexibility. ARM’s ARMv8-A architecture includes a set of coprocessor registers for managing the PMU, which can be accessed using the MCR (Move to Coprocessor Register) and MRC (Move from Coprocessor Register) instructions.
To enable PMU counters, developers must first configure the PMU Control Register (PMCR). This register controls global PMU settings, such as enabling counters and resetting their values. The following assembly code demonstrates how to write to the PMCR:
/* PMU Control Register (PMCR) Configuration */
TFUNC write_PMCR
mcr p15, #0, r0, c9, c12, #0 /* Write value in r0 to PMCR */
bx lr /* Return from function */
ENDFUNC write_PMCR
In this example, the mcr instruction writes the value in register r0 to the PMCR. The p15 operand specifies the coprocessor, while c9 and c12 identify the PMCR. The #0 operands indicate the opcode and coprocessor-specific options.
After configuring the PMCR, developers can program individual event counters by writing to the PMU Event Selection Registers (PMSELR) and PMU Event Count Registers (PMXEVTYPER). These registers allow developers to specify which events to monitor and to read the corresponding counter values. The following code snippet illustrates how to configure an event counter:
/* PMU Event Counter Configuration */
TFUNC configure_counter
mov r0, #event_number /* Load event number into r0 */
mcr p15, #0, r0, c9, c12, #5 /* Write event number to PMSELR */
mov r0, #0x1 /* Enable counter */
mcr p15, #0, r0, c9, c12, #1 /* Write to PMCNTENSET */
ENDFUNC configure_counter
In this example, event_number corresponds to the desired performance event, as defined in the Cortex-A55 TRM. The mcr instructions configure the event counter and enable it via the PMCNTENSET register.
Kernel-Level Support and Debugging
For systems running Linux, ensuring kernel-level support for the Cortex-A55 PMU is essential. Developers should verify that the kernel’s perf subsystem includes the necessary drivers and configurations for the Cortex-A55. If support is lacking, developers may need to modify the kernel source code or apply patches to enable PMU functionality.
Debugging PMU access issues often involves examining kernel logs and using tools like perf to diagnose problems. For example, running perf list should display the available PMU events for the Cortex-A55. If the expected events are missing, this indicates a configuration issue that must be addressed.
Summary of Solutions
The following table summarizes the key steps for resolving Cortex-A55 PMU counter access issues:
| Step | Description | Tools/Resources |
|---|---|---|
| 1 | Update configuration files for Cortex-A55 PMU | Cortex-A55 TRM, perfmon2/PAPI source code |
| 2 | Recompile tools with updated configurations | GCC, Makefiles |
| 3 | Validate PMU counter access | Test cases, perf tool |
| 4 | Implement direct PMU register access | Assembly code, Cortex-A55 TRM |
| 5 | Verify kernel-level PMU support | Linux kernel source code, dmesg logs |
By following these steps, developers can overcome the challenges of accessing Cortex-A55 PMU counters and leverage the full potential of ARM’s performance monitoring capabilities. Whether extending existing tools or implementing custom solutions, a thorough understanding of the Cortex-A55’s PMU architecture is key to achieving accurate and reliable performance analysis.
