Decoding AXI Byte Addressing to DRAM Addressing on ARM Cortex-A53

Understanding AXI-to-DRAM Address Mapping in ARM Cortex-A53 Systems

The ARM Cortex-A53 processor, commonly used in systems like the Zynq UltraScale+ MPSoC, relies on the Advanced eXtensible Interface (AXI) for memory transactions. AXI is a byte-addressable protocol, meaning it uses byte-level granularity for addressing memory. However, DRAM (Dynamic Random Access Memory) operates on a different addressing scheme, which is organized into ranks, banks, rows, and columns. This discrepancy necessitates a mapping mechanism to translate AXI byte addresses into DRAM-specific addresses. This post delves into the intricacies of this mapping process, focusing on the ARM Cortex-A53 and DDR4 memory systems.

AXI Byte Addressing and DRAM Addressing Fundamentals

AXI byte addressing is a linear addressing scheme where each byte in the memory space is assigned a unique address. For a 64-bit data bus, the lower three bits of the AXI address (bits [2:0]) represent the byte index within the 64-bit word. These bits are typically masked out when translating to DRAM addressing because DRAM accesses are performed at the granularity of a full word (64 bits in this case).

DRAM addressing, on the other hand, is hierarchical and consists of multiple levels: rank, bank group, bank, row, and column. Each level serves a specific purpose in organizing and accessing memory efficiently. For example, the row address selects a specific row within a bank, and the column address selects a specific column within that row. The bank address selects a specific bank within a bank group, and the bank group address selects a specific group of banks. The rank address selects a specific rank of memory chips.

The challenge lies in mapping the linear AXI byte address to this hierarchical DRAM address structure. This mapping is not straightforward because the AXI address does not inherently contain information about the DRAM hierarchy. Instead, the mapping must be derived based on the DRAM configuration and the specific implementation of the memory controller.

Conflicting Information in Documentation and Forums

One of the primary sources of confusion in this mapping process is the conflicting information provided in various documentation and forum threads. For instance, the Xilinx forums suggest a specific mapping where the AXI address bits are directly mapped to DRAM address bits, such as Rank[34], BankGroup[33:32], Banks[31:30], Row[29:13], Column[12:3], and byteIndex[2:0]. However, this mapping does not align with the information provided in the Xilinx UltraScale+ documentation (UG 1087), which describes the ADDRMAP registers as an intermediate step in the mapping process.

The ADDRMAP registers are used to configure how the High-Speed Interface (HIF) address bits are mapped to DRAM address bits. The HIF address is an intermediate representation that bridges the gap between the AXI byte address and the DRAM address. According to UG 1087, the ADDRMAP registers define the relationship between the HIF address bits and the DRAM address bits. However, the documentation also contains conflicting equations (17-1 and 17-3) that describe the mapping process, leading to further confusion.

Additionally, Xilinx Answer Record 71359 states that the HIF[0] bit corresponds to the DRAM column bit 0. It also suggests that to map from the byte-addressable AXI to DRAM addressing, three bits should be added to the HIF ADDRMAP representation for a 64-bit data bus. This implies that the AXI address should be shifted left by three bits to align with the HIF address, but this is not explicitly stated in the documentation.

Decoding Logical Addresses to DRAM Addressing

The ultimate goal of this mapping process is to decode a given logical AXI address (e.g., 0x8BE007620) into its corresponding DRAM address components: rank, bank group, bank, row, and column. To achieve this, we need to understand the relationship between the AXI address, the HIF address, and the DRAM address.

The AXI address is a 36-bit value in this case, with the lower three bits representing the byte index. These three bits are masked out when translating to the HIF address, resulting in a 33-bit HIF address. The HIF address is then mapped to the DRAM address using the ADDRMAP registers. The ADDRMAP registers define how each HIF address bit corresponds to a specific DRAM address bit, such as rank, bank group, bank, row, or column.

For example, if the ADDRMAP registers are configured such that HIF[0] maps to DRAM column bit 0, HIF[1] maps to DRAM column bit 1, and so on, then the HIF address can be directly translated into the DRAM address by following the mapping defined by the ADDRMAP registers. However, this mapping is not always straightforward, as the ADDRMAP registers can be configured in various ways depending on the specific DRAM configuration and memory controller implementation.

Resolving the Confusion: A Step-by-Step Approach

To resolve the confusion and accurately map AXI byte addresses to DRAM addresses, we need to follow a systematic approach that takes into account the DRAM configuration, the ADDRMAP register settings, and the specific implementation of the memory controller. Here are the steps to achieve this:

1. Determine the DRAM Configuration: The first step is to understand the DRAM configuration, including the number of ranks, bank groups, banks, rows, and columns. This information is typically provided in the DRAM datasheet and is essential for defining the ADDRMAP register settings.

2. Configure the ADDRMAP Registers: The ADDRMAP registers define how the HIF address bits are mapped to the DRAM address bits. These registers should be configured based on the DRAM configuration and the specific requirements of the memory controller. The configuration should ensure that the HIF address bits are correctly mapped to the DRAM rank, bank group, bank, row, and column bits.

3. Map the AXI Address to the HIF Address: The AXI address is a byte-addressable 36-bit value, with the lower three bits representing the byte index. To map the AXI address to the HIF address, the lower three bits should be masked out, resulting in a 33-bit HIF address. This HIF address is then used as input to the ADDRMAP registers.

4. Translate the HIF Address to the DRAM Address: Using the ADDRMAP register settings, the HIF address is translated into the DRAM address. This involves mapping each HIF address bit to the corresponding DRAM address bit, such as rank, bank group, bank, row, or column. The specific mapping depends on the ADDRMAP register configuration.

5. Verify the Mapping: Once the mapping is complete, it is essential to verify that the AXI address is correctly translated into the DRAM address. This can be done by comparing the expected DRAM address with the actual DRAM address generated by the memory controller. Any discrepancies should be investigated and resolved by adjusting the ADDRMAP register settings.

Example: Decoding a Logical AXI Address

Let’s consider an example where we need to decode the logical AXI address 0x8BE007620 into its corresponding DRAM address components. Here’s how we can achieve this:

1. Mask the Lower Three Bits: The AXI address 0x8BE007620 is a 36-bit value. The lower three bits (bits [2:0]) represent the byte index and should be masked out. This results in a 33-bit HIF address: 0x45F003B10.

2. Configure the ADDRMAP Registers: Based on the DRAM configuration (32 GB DDR4 with 17 row address bits, 10 column bits, 2 bank group bits, and 2 bank bits), the ADDRMAP registers should be configured to map the HIF address bits to the DRAM address bits. For example, HIF[0] could be mapped to DRAM column bit 0, HIF[1] to DRAM column bit 1, and so on.

3. Translate the HIF Address to the DRAM Address: Using the ADDRMAP register settings, the HIF address 0x45F003B10 is translated into the DRAM address. For instance, HIF[0] maps to DRAM column bit 0, HIF[1] maps to DRAM column bit 1, HIF[2] maps to DRAM column bit 2, and so on. The specific mapping depends on the ADDRMAP register configuration.

4. Extract the DRAM Address Components: Once the HIF address is translated into the DRAM address, the individual components (rank, bank group, bank, row, and column) can be extracted. For example, if the ADDRMAP registers are configured such that HIF[0] maps to DRAM column bit 0, HIF[1] maps to DRAM column bit 1, and so on, then the DRAM column bits can be directly extracted from the HIF address.

5. Verify the Mapping: Finally, the mapping should be verified by comparing the expected DRAM address with the actual DRAM address generated by the memory controller. Any discrepancies should be investigated and resolved by adjusting the ADDRMAP register settings.

Conclusion

Mapping AXI byte addresses to DRAM addresses in ARM Cortex-A53 systems is a complex process that requires a deep understanding of both the AXI protocol and the DRAM addressing scheme. The key to success lies in correctly configuring the ADDRMAP registers and following a systematic approach to translate the AXI address into the DRAM address. By carefully analyzing the DRAM configuration, configuring the ADDRMAP registers, and verifying the mapping, it is possible to accurately decode logical AXI addresses into their corresponding DRAM address components. This process is essential for optimizing memory performance and ensuring reliable system operation in ARM Cortex-A53-based systems.