Determining Page Size on ARMv8 for Non-Secure EL1 Stage 1

ARMv8 Page Size Determination Challenges in Non-Secure EL1 Stage 1

Determining the page size in ARMv8 architecture, particularly for Non-Secure EL1 Stage 1, is a critical task for system developers and kernel programmers. The ARMv8 architecture supports multiple page sizes, and the actual page size used can vary depending on the implementation and configuration of the Memory Management Unit (MMU). The challenge arises when developers need to programmatically determine the page size at runtime, especially within the context of the Linux kernel. This issue is compounded by the fact that the ARMv8 architecture does not provide a direct register or instruction to read the page size directly. Instead, developers must rely on indirect methods, such as using the Address Translation (AT) instructions and parsing the resulting translation attributes.

The primary method discussed involves using the AT S1E1R instruction to perform a stage 1 translation and then reading the Physical Address Register (PAR_EL1) to obtain the translation attributes. However, the PAR_EL1 register does not explicitly provide the page size, necessitating further interpretation of the attributes to deduce the page size. Additionally, the Translation Lookaside Buffer (TLB) entries could be used to determine the page size, but this approach is fraught with complexities, such as TLB entry invalidation and the difficulty of accessing TLB RAM directly.

Memory Management Unit Configuration and Implementation-Dependent Behavior

The root cause of the difficulty in determining the page size lies in the implementation-dependent behavior of the ARMv8 MMU and the lack of a dedicated register or instruction to directly report the page size. The ARMv8 architecture allows for flexibility in MMU configuration, enabling different page sizes to be used depending on the system’s requirements. This flexibility is beneficial for optimizing memory usage and performance but complicates the task of programmatically determining the page size.

The AT S1E1R instruction, which performs a stage 1 translation for a given virtual address, stores the translation result in the PAR_EL1 register. While the PAR_EL1 register contains fields for attributes such as the physical address, memory attributes, and the Non-Secure (NS) bit, it does not include a direct field for the page size. Instead, the page size must be inferred from the attributes, which can be non-trivial.

Furthermore, the TLB, which caches recent translations, could theoretically be used to determine the page size. However, accessing the TLB directly is not straightforward, as it requires knowledge of the TLB’s internal structure and the ability to read its contents without causing side effects, such as invalidating entries. This approach is further complicated by the possibility of TLB entries being flushed between the time a translation is performed and the time the TLB is read.

Leveraging Address Translation and PAR_EL1 for Page Size Determination

To determine the page size on ARMv8 for Non-Secure EL1 Stage 1, developers can use a combination of the AT S1E1R instruction and the PAR_EL1 register. The process involves performing a stage 1 translation for a given virtual address and then interpreting the attributes stored in the PAR_EL1 register to deduce the page size. Here is a detailed step-by-step guide to achieving this:

1. Perform Stage 1 Translation Using AT S1E1R: The first step is to execute the AT S1E1R instruction with the virtual address for which the page size needs to be determined. This instruction performs a stage 1 translation and stores the result in the PAR_EL1 register.

   __asm__ volatile ("at s1e1r, %0" : : "r" (buf));
   

2. Read the PAR_EL1 Register: After executing the AT S1E1R instruction, the next step is to read the contents of the PAR_EL1 register. This register contains the translation attributes, including the physical address, memory attributes, and the Non-Secure (NS) bit.

   __asm__ volatile ("mrs %0, PAR_EL1\n" : "=r" (par_el1));
   

3. Interpret the PAR_EL1 Attributes: The PAR_EL1 register does not directly provide the page size, but the page size can be inferred from the attributes. Specifically, the memory attributes field in the PAR_EL1 register can be used to determine the page size. The memory attributes include information about the memory type, cacheability, and shareability, which can be mapped to the page size based on the ARMv8 architecture specifications.

4. Map Attributes to Page Size: The final step is to map the memory attributes obtained from the PAR_EL1 register to the corresponding page size. This mapping requires a deep understanding of the ARMv8 architecture and the specific implementation of the MMU. The following table provides an example of how memory attributes can be mapped to page sizes:

   Memory Attribute Field	Page Size
   AttrIndex[2:0] = 0b000	4KB
   AttrIndex[2:0] = 0b001	64KB
   AttrIndex[2:0] = 0b010	16KB
   AttrIndex[2:0] = 0b011	1MB
   AttrIndex[2:0] = 0b100	2MB
   AttrIndex[2:0] = 0b101	512MB
   AttrIndex[2:0] = 0b110	1GB
   AttrIndex[2:0] = 0b111	Reserved

5. Handle Implementation-Specific Variations: It is important to note that the mapping of memory attributes to page sizes can vary depending on the specific implementation of the ARMv8 architecture. Therefore, developers should consult the documentation for their specific processor to ensure accurate mapping.

6. Consider TLB Invalidation and Cache Coherency: When using the TLB to determine the page size, developers must be cautious about TLB invalidation and cache coherency. TLB entries can be invalidated at any time, and reading the TLB directly can lead to inconsistent results. To mitigate this, developers should ensure that the TLB is not invalidated between the time the translation is performed and the time the TLB is read.

7. Implement Data Synchronization Barriers: To ensure that the translation results are consistent and that the TLB entries are not invalidated prematurely, developers should implement data synchronization barriers. These barriers ensure that all previous memory operations are completed before proceeding to the next step.

   __asm__ volatile ("dsb sy");
   

8. Cache Management: In some cases, it may be necessary to manage the cache to ensure that the translation results are accurate. This can involve invalidating the cache or ensuring that the cache is coherent with the TLB.

   __asm__ volatile ("ic iallu");
   

9. Testing and Validation: Finally, developers should thoroughly test and validate their implementation to ensure that the page size is determined accurately. This can involve testing with different page sizes and configurations to verify that the method works correctly in all scenarios.

By following these steps, developers can accurately determine the page size on ARMv8 for Non-Secure EL1 Stage 1, even in the absence of a direct register or instruction to report the page size. This method leverages the existing ARMv8 architecture features and provides a reliable way to infer the page size from the translation attributes stored in the PAR_EL1 register.

Conclusion

Determining the page size on ARMv8 for Non-Secure EL1 Stage 1 is a complex task that requires a deep understanding of the ARMv8 architecture and the specific implementation of the MMU. By using the AT S1E1R instruction and the PAR_EL1 register, developers can infer the page size from the translation attributes. However, this method requires careful interpretation of the attributes and consideration of implementation-specific variations. Additionally, developers must be cautious about TLB invalidation and cache coherency to ensure accurate results. By following the detailed steps outlined in this guide, developers can successfully determine the page size and ensure reliable system implementations on ARMv8 architectures.