Identifying PMU Version and Features in ARM Cortex-A73 Processors
The Performance Monitoring Unit (PMU) in ARMv8 architectures is a critical component for profiling and debugging system performance. However, determining the specific PMU version and features implemented in a particular ARM Cortex-A73 processor can be challenging due to the variability in ARMv8 implementations. The ARM Architecture Reference Manual (ARM ARM) often uses conditional language such as "If xxx is implemented," which leaves developers uncertain about the exact capabilities of their hardware.
To identify whether a specific ARM Cortex-A73 processor implements a particular PMU version (e.g., PMUv3.1) or features (e.g., ARMv8.6-ECV or ARMv8.5-PMU), developers must consult the processor’s technical reference manual (TRM) and system registers. The TRM for the Cortex-A73 provides detailed information about the PMU, but it may not explicitly state the PMU version. Instead, developers can use the ID_DFR0 (Debug Feature Register 0) to determine the PMU implementation.
The ID_DFR0 register is part of the ARMv8 system registers and provides information about the debug and performance monitoring features supported by the processor. Specifically, bits [27:24] of ID_DFR0 indicate the PMU version implemented. For example, a value of 0x5 in these bits corresponds to PMUv3.1. By reading this register, developers can confirm the PMU version and features available on their Cortex-A73 processor.
Additionally, the ARMv8 architecture allows for optional extensions and features, which may or may not be implemented in a specific processor. To determine whether a particular feature (e.g., ARMv8.6-ECV) is supported, developers should check the relevant feature registers, such as ID_AA64MMFR2_EL1 for memory model features or ID_AA64DFR0_EL1 for debug and trace features. These registers provide a detailed breakdown of the implemented features and extensions.
In summary, identifying the PMU version and features in an ARM Cortex-A73 processor requires a combination of consulting the TRM and reading system registers such as ID_DFR0 and ID_AA64DFR0_EL1. These steps ensure that developers have a clear understanding of the PMU capabilities and can configure it appropriately for performance monitoring tasks.
Understanding PMEVTYPER.P/U Configuration for Event Counting in EL0 and EL1
The PMU in ARMv8 architectures provides event counters that can be configured to count specific events at different exception levels (ELs). The PMEVTYPER register controls the behavior of these counters, including whether events are counted in EL0 (user space) or EL1 (kernel space). The PMEVTYPER.P and PMEVTYPER.U bits are particularly important for configuring event counting in these exception levels.
The PMEVTYPER.P bit controls whether events are counted in EL1 (kernel space). When this bit is set to 1, events occurring in EL1 are counted. Conversely, when it is set to 0, events in EL1 are ignored. Similarly, the PMEVTYPER.U bit controls event counting in EL0 (user space). Setting this bit to 1 enables counting of events in EL0, while setting it to 0 disables counting in EL0.
This configuration allows developers to isolate performance monitoring to specific exception levels. For example, if a developer wants to measure the performance of a user-space application without interference from kernel activities, they can set PMEVTYPER.P to 0 and PMEVTYPER.U to 1. This ensures that only events occurring in EL0 are counted, providing a clear view of the application’s performance.
Conversely, if the goal is to measure kernel performance without interference from user-space applications, developers can set PMEVTYPER.P to 1 and PMEVTYPER.U to 0. This configuration counts only events in EL1, allowing developers to focus on kernel-level performance issues.
It is important to note that the PMU does not provide complete isolation between exception levels. For example, if a system call is made from EL0 to EL1, the PMU will count events in both exception levels unless explicitly configured otherwise. Therefore, developers must carefully consider their performance monitoring goals and configure the PMEVTYPER register accordingly.
In addition to the PMEVTYPER.P and PMEVTYPER.U bits, the PMU provides other configuration options, such as event filtering and interrupt generation. These features allow developers to fine-tune their performance monitoring setup and gather detailed insights into system behavior.
Configuring and Validating PMU Event Counting for Accurate Performance Analysis
To effectively use the PMU for performance analysis, developers must follow a systematic approach to configure and validate event counting. This involves setting up the PMEVTYPER register, enabling event counters, and verifying that the counters are functioning as expected.
The first step is to configure the PMEVTYPER register for the desired event counting behavior. As discussed earlier, this involves setting the PMEVTYPER.P and PMEVTYPER.U bits to control event counting in EL1 and EL0, respectively. Developers should also select the specific event to be counted by setting the PMEVTYPER.EVTCOUNT field. The ARMv8 architecture defines a wide range of events that can be counted, such as cycle counts, instruction retirements, and cache misses.
Once the PMEVTYPER register is configured, developers must enable the event counter by setting the corresponding bit in the PMCNTENSET register. This register controls which event counters are active. For example, setting bit 0 in PMCNTENSET enables counter 0, while setting bit 1 enables counter 1, and so on.
After enabling the event counters, developers should start the counters by setting the PMCR.E bit in the PMCR (Performance Monitor Control Register). This bit globally enables all event counters. Developers can also reset the counters by setting the PMCR.C bit, which clears all counter values to zero.
To validate that the event counters are functioning correctly, developers should run a known workload and compare the counter values to expected results. For example, if the goal is to measure the number of instructions executed in a user-space application, developers can run a simple loop and verify that the instruction counter matches the expected count.
If the counter values do not match expectations, developers should check the PMEVTYPER configuration and ensure that the correct event is being counted. They should also verify that the counters are enabled and started correctly. Additionally, developers should check for any potential issues with event filtering or interrupt generation that could affect counter accuracy.
In conclusion, configuring and validating PMU event counting requires careful attention to detail and a thorough understanding of the PMU registers and their functions. By following a systematic approach, developers can ensure accurate performance analysis and gain valuable insights into system behavior.
