VDDCE and VDDPE Power Sequencing Violation in Power Down Mode
The core issue revolves around the improper power pin connection strategy for the Arm Artisan 14nm 14LPP High-Speed Single-Port SRAM, specifically concerning the VDDCE and VDDPE power pins. The design team plans to connect VDDCE and VDDPE to the same power net, which simplifies the power distribution network but introduces significant risks during power down mode. According to the Arm Artisan 14nm 14LPP Power Management document, VDDCE and VDDPE must follow a strict power sequencing protocol during power down and power up operations. Specifically, VDDPE must be powered down before VDDCE, and VDDPE must be powered up after VDDCE. This sequencing is critical to prevent forward biasing of PN diodes in the SRAM’s internal circuitry, where P-diffusion regions are connected to VDDPE and N-WELL regions are connected to VDDCE. Forward biasing these diodes can lead to leakage currents, potential latch-up conditions, and permanent damage to the SRAM cells.
The design team’s approach of tying VDDCE and VDDPE to the same power net violates this sequencing requirement, as both pins would power up and power down simultaneously. This creates a high-risk scenario, particularly during power down mode, where the absence of proper sequencing can cause unintended electrical behavior in the SRAM. The issue is further compounded by the fact that the SRAM is being used in a power-gated configuration, where external power gating is applied to control the SRAM’s power states. Without proper sequencing, the SRAM’s internal power domains may not transition cleanly between states, leading to data corruption, increased power consumption, and potential reliability issues over time.
Forward Biasing of PN Diodes Due to Simultaneous Power Transitions
The primary cause of the issue lies in the simultaneous power transitions of VDDCE and VDDPE, which directly violates the sequencing requirements outlined in the Arm Artisan 14nm 14LPP Power Management document. When VDDCE and VDDPE are connected to the same power net, both pins experience identical voltage transitions during power up and power down operations. This simultaneous transition disrupts the internal biasing of the SRAM’s PN junctions, leading to forward biasing conditions.
In the SRAM’s internal structure, P-diffusion regions are connected to VDDPE, while N-WELL regions are connected to VDDCE. These regions form PN junctions that are designed to operate under specific biasing conditions. During normal operation, the voltage difference between VDDCE and VDDPE ensures that these PN junctions remain reverse-biased, preventing current flow across the junctions. However, when VDDCE and VDDPE transition simultaneously, the voltage difference between these pins can become insufficient to maintain reverse biasing, causing the PN junctions to become forward-biased. This forward biasing allows current to flow across the junctions, leading to increased leakage currents and potential latch-up conditions.
Additionally, the lack of proper sequencing can cause transient voltage mismatches between VDDCE and VDDPE during power transitions. These mismatches can result in unintended current paths within the SRAM, further exacerbating the risk of electrical failures. The forward biasing issue is particularly problematic during power down mode, where the SRAM’s internal circuitry is designed to enter a low-power state. If the PN junctions are forward-biased during this transition, the SRAM may fail to enter the intended power state, leading to increased power consumption and potential data corruption.
Implementing Independent Power Control for VDDCE and VDDPE
To address the power sequencing violation and prevent forward biasing of PN diodes, the design team must implement independent power control for VDDCE and VDDPE. This involves separating the power nets for VDDCE and VDDPE and introducing a power sequencing controller to manage the timing of power transitions. The power sequencing controller should ensure that VDDPE is powered down before VDDCE during power down operations and that VDDPE is powered up after VDDCE during power up operations. This sequencing can be achieved using a state machine or a dedicated power management IC that controls the enable signals for the power gates connected to VDDCE and VDDPE.
The power sequencing controller should be designed to account for the specific timing requirements outlined in the Arm Artisan 14nm 14LPP Power Management document. This includes ensuring that the delay between powering down VDDPE and VDDCE is sufficient to prevent forward biasing of PN junctions. Similarly, during power up, the delay between powering up VDDCE and VDDPE should be carefully calibrated to avoid transient voltage mismatches. The controller should also include monitoring circuits to detect and correct any deviations from the intended power sequencing, ensuring reliable operation under all conditions.
In addition to implementing independent power control, the design team should perform extensive simulation and verification to validate the power sequencing behavior. This includes running power-up and power-down sequences in a simulation environment to verify that the timing requirements are met and that no forward biasing conditions occur. The team should also perform corner case analysis to ensure that the power sequencing controller operates correctly under varying process, voltage, and temperature conditions. By implementing these measures, the design team can mitigate the risks associated with improper power pin connections and ensure the reliable operation of the Arm Artisan 14nm 14LPP High-Speed Single-Port SRAM in their SoC design.
