Full Adder Output Delay Discrepancy During Simultaneous Input Transitions
The issue revolves around the behavior of the full adder cell from the ARM standard library during timing simulations. Specifically, the output delay of the carry-out signal (CO) exhibits inconsistent behavior depending on the timing of the input transitions. When the inputs A and B fall simultaneously, the CO signal transitions instantaneously without any delay. However, when A and B fall at different times or rise simultaneously, the CO signal exhibits the expected output delay as annotated in the SDF file or the default delay specified in the library.
This discrepancy is particularly problematic because it leads to hold time violations in the design during timing simulations, even though static timing analysis (STA) does not report any issues. The full adder cell’s specify block, which defines the timing arcs and delays, appears to be missing or incorrectly configured for the case where both A and B fall simultaneously. This behavior has been observed consistently across multiple full adder cells in the ARM standard library and has been verified using industry-standard simulation tools like VCS and IES.
The core of the problem lies in the interaction between the specify block, the SDF annotation, and the simulator’s handling of simultaneous input transitions. The specify block is responsible for defining the timing relationships between the inputs and outputs of the cell, including the propagation delays and any conditional delays based on input transitions. In this case, the specify block seems to lack a proper definition for the scenario where both A and B fall simultaneously, leading to the simulator bypassing the expected delay.
Missing Specify Block Definitions and Simultaneous Input Transition Handling
The root cause of the issue can be traced back to two primary factors: the absence of proper specify block definitions for simultaneous input transitions and the simulator’s handling of such transitions. The specify block in the full adder cell is likely missing the necessary timing arcs to handle the case where both A and B fall at the same time. This omission causes the simulator to default to an instantaneous transition for the CO signal, as it does not have any delay information to apply in this scenario.
Additionally, the simulator’s internal logic for handling simultaneous input transitions may contribute to the issue. When multiple inputs transition simultaneously, the simulator must decide how to process these transitions and apply the corresponding delays. In some cases, the simulator may prioritize one input transition over the other, leading to unexpected behavior. This is particularly true if the specify block does not explicitly define how simultaneous transitions should be handled.
Another potential cause is the interaction between the SDF annotation and the specify block. The SDF file contains the timing information for the cell, including the delays for different input-to-output paths. However, if the specify block does not define the timing arcs for simultaneous input transitions, the SDF annotation may not be applied correctly, leading to the observed discrepancy in output delays.
The issue is further compounded by the fact that STA tools do not typically model the behavior of simultaneous input transitions in the same way as timing simulators. STA tools rely on static timing models and do not simulate the actual behavior of the cell, which is why they do not report any hold time violations. This discrepancy between STA and timing simulation results can make it difficult to identify and resolve the issue during the design verification process.
Correcting Specify Block Definitions and Simulator Configuration
To address the issue, several steps can be taken to correct the specify block definitions and ensure proper handling of simultaneous input transitions during timing simulations. The first step is to review and modify the specify block in the full adder cell to include explicit timing arcs for simultaneous input transitions. This involves adding the necessary delay definitions for the case where both A and B fall at the same time, ensuring that the CO signal exhibits the expected output delay.
The specify block should be updated to include conditional timing arcs that account for all possible input transition scenarios, including simultaneous transitions. This can be achieved by using conditional statements within the specify block to define the delays for different input combinations. For example, the specify block can be modified to include a conditional delay for the case where both A and B fall simultaneously, ensuring that the CO signal transitions with the correct delay.
In addition to modifying the specify block, it may be necessary to adjust the simulator configuration to ensure proper handling of simultaneous input transitions. This can involve enabling specific simulation options that control how the simulator processes simultaneous transitions. For example, some simulators offer options to prioritize certain input transitions or to apply delays in a specific order when multiple inputs transition simultaneously. These options can be used to ensure that the simulator applies the correct delays to the CO signal, even when A and B fall at the same time.
Another approach is to use a custom timing model for the full adder cell that explicitly defines the behavior for simultaneous input transitions. This can be done by creating a custom Verilog or VHDL model for the full adder cell that includes the necessary timing arcs and delay definitions. The custom model can then be used in place of the standard library cell during timing simulations, ensuring that the CO signal exhibits the expected output delay in all scenarios.
Finally, it is important to validate the changes by running extensive timing simulations to verify that the issue has been resolved. This involves creating test cases that cover all possible input transition scenarios, including simultaneous transitions, and verifying that the CO signal transitions with the correct delay in each case. The simulation results should be compared against the expected behavior to ensure that the specify block modifications and simulator configuration adjustments have effectively addressed the issue.
In conclusion, the timing simulation anomaly in the ARM standard library full adder cell is caused by missing specify block definitions for simultaneous input transitions and the simulator’s handling of such transitions. By correcting the specify block definitions, adjusting the simulator configuration, and validating the changes through extensive timing simulations, the issue can be resolved, ensuring that the CO signal exhibits the expected output delay in all scenarios.
